diff options
authorAdam Kropelin <akropel1@rochester.rr.com>2005-09-16 19:28:19 -0700
committerLinus Torvalds <torvalds@g5.osdl.org>2005-09-17 11:50:03 -0700
commit06c6d271f41ffa20f2dadc9bfe100a89f7f1dd1d (patch)
parentc2fa4f4ad8ddf4b9fac344f1da7a25d4868f08f5 (diff)
[PATCH] shpchp: Use dword accessors for PCI_ROM_ADDRESS
PCI_ROM_ADDRESS is a 32 bit register and as such should be accessed using pci_bus_{read,write}_config_dword(). A recent audit of drivers/ turned up several cases of byte- and word-sized accesses. The harmful ones were fixed by Linus directly. This patches up one of the remaining harmless-but-still-wrong cases caught in the dragnet. Signed-off-by: Adam Kropelin <akropel1@rochester.rr.com> Cc: <kristen.c.accardi@intel.com> Cc: Greg KH <greg@kroah.com> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
1 files changed, 1 insertions, 2 deletions
diff --git a/drivers/pci/hotplug/shpchp_ctrl.c b/drivers/pci/hotplug/shpchp_ctrl.c
index 783b5abb0717..91c9903e621f 100644
--- a/drivers/pci/hotplug/shpchp_ctrl.c
+++ b/drivers/pci/hotplug/shpchp_ctrl.c
@@ -2824,8 +2824,7 @@ static int configure_new_function (struct controller * ctrl, struct pci_func * f
/* Disable ROM base Address */
- temp_word = 0x00L;
- rc = pci_bus_write_config_word (pci_bus, devfn, PCI_ROM_ADDRESS, temp_word);
+ rc = pci_bus_write_config_dword (pci_bus, devfn, PCI_ROM_ADDRESS, 0x00);
/* Set HP parameters (Cache Line Size, Latency Timer) */
rc = shpchprm_set_hpp(ctrl, func, PCI_HEADER_TYPE_NORMAL);

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