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authorNicolas Pitre <nico@cam.org>2008-09-16 17:05:53 (GMT)
committerNicolas Pitre <nico@cam.org>2009-03-16 01:01:20 (GMT)
commit5f0fbf9ecaf354fa4bbf266fffdea2ea3d14a0ed (patch)
tree9f0c59760b2bec510519118ddb17d4b15db473f5 /Documentation/arm
parent1522ac3ec95ff0230e7aa516f86b674fdf72866c (diff)
[ARM] fixmap support
This is the minimum fixmap interface expected to be implemented by architectures supporting highmem. We have a second level page table already allocated and covering 0xfff00000-0xffffffff because the exception vector page is located at 0xffff0000, and various cache tricks already use some entries above 0xffff0000. Therefore the PTEs covering 0xfff00000-0xfffeffff are free to be used. However the XScale cache flushing code already uses virtual addresses between 0xfffe0000 and 0xfffeffff. So this reserves the 0xfff00000-0xfffdffff range for fixmap stuff. The Documentation/arm/memory.txt information is updated accordingly, including the information about the actual top of DMA memory mapping region which didn't match the code. Signed-off-by: Nicolas Pitre <nico@marvell.com>
Diffstat (limited to 'Documentation/arm')
-rw-r--r--Documentation/arm/memory.txt9
1 files changed, 8 insertions, 1 deletions
diff --git a/Documentation/arm/memory.txt b/Documentation/arm/memory.txt
index dc60455..43cb100 100644
--- a/Documentation/arm/memory.txt
+++ b/Documentation/arm/memory.txt
@@ -29,7 +29,14 @@ ffff0000 ffff0fff CPU vector page.
CPU supports vector relocation (control
register V bit.)
-ffc00000 fffeffff DMA memory mapping region. Memory returned
+fffe0000 fffeffff XScale cache flush area. This is used
+ in proc-xscale.S to flush the whole data
+ cache. Free for other usage on non-XScale.
+
+fff00000 fffdffff Fixmap mapping region. Addresses provided
+ by fix_to_virt() will be located here.
+
+ffc00000 ffefffff DMA memory mapping region. Memory returned
by the dma_alloc_xxx functions will be
dynamically mapped here.

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