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authorHaiying Wang <Haiying.Wang@freescale.com>2009-05-01 19:40:47 (GMT)
committerKumar Gala <galak@kernel.crashing.org>2009-05-19 05:50:22 (GMT)
commit06c4435021f4856261edd01e2691071edeb8fa51 (patch)
tree54e0a8be20b73d328df5aeae874e725ea7bbc80e /Documentation/powerpc
parentea5130dcb438840d64a168b67dd221e4d46246b8 (diff)
powerpc/qe: update risc allocation for QE
Change the RISC allocation to macros instead of enum, add function to read the number of risc engines from the new property "fsl,qe-num-riscs" under the qe node in dts. Add new property "fsl,qe-num-riscs" description in qe.txt Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com> Acked-by: Timur Tabi <timur@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Diffstat (limited to 'Documentation/powerpc')
-rw-r--r--Documentation/powerpc/dts-bindings/fsl/cpm_qe/qe.txt1
1 files changed, 1 insertions, 0 deletions
diff --git a/Documentation/powerpc/dts-bindings/fsl/cpm_qe/qe.txt b/Documentation/powerpc/dts-bindings/fsl/cpm_qe/qe.txt
index 78790d5..39b5d1f 100644
--- a/Documentation/powerpc/dts-bindings/fsl/cpm_qe/qe.txt
+++ b/Documentation/powerpc/dts-bindings/fsl/cpm_qe/qe.txt
@@ -17,6 +17,7 @@ Required properties:
- model : precise model of the QE, Can be "QE", "CPM", or "CPM2"
- reg : offset and length of the device registers.
- bus-frequency : the clock frequency for QUICC Engine.
+- fsl,qe-num-riscs: define how many RISC engines the QE has.
Recommended properties
- brg-frequency : the internal clock source frequency for baud-rate

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