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authorJesse Barnes <jbarnes@virtuousgeek.org>2009-01-09 13:56:14 -0800
committerDave Airlie <airlied@linux.ie>2009-01-16 18:40:57 +1000
commit712531bfe95be42a672ebab51b55580e7d92c464 (patch)
treec792aadeee7059e01ea5a3d5d2b2ab63b8cd8d26 /drivers/gpu/drm/i915/intel_display.c
parent40a518d9f1fd8ed1061b8b4e2ce8a44794f4eb03 (diff)
drm: handle depth & bpp changes correctly
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Eric Anholt <eric@anholt.net> Signed-off-by: Dave Airlie <airlied@linux.ie>
Diffstat (limited to 'drivers/gpu/drm/i915/intel_display.c')
-rw-r--r--drivers/gpu/drm/i915/intel_display.c2
1 files changed, 2 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 8ccb9c3ab868..4372acff5a01 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -401,6 +401,8 @@ intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
I915_WRITE(dspstride, crtc->fb->pitch);
dspcntr = I915_READ(dspcntr_reg);
+ /* Mask out pixel format bits in case we change it */
+ dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
switch (crtc->fb->bits_per_pixel) {
case 8:
dspcntr |= DISPPLANE_8BPP;

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