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authorNicolas Ferre <nicolas.ferre@atmel.com>2010-10-14 16:51:36 +0200
committerNicolas Ferre <nicolas.ferre@atmel.com>2010-10-26 11:32:47 +0200
commitef4d63e6f51d9669e247c47b670a83511b98eb68 (patch)
tree35871307329b7477c87486634925c6050b28ec66 /arch
parent184c82e853704ee98e729af0f36a8539355c0e2e (diff)
AT91: trivial: align comment of at91sam9g20_reset with one more tab
Preparing next patch with longer names Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Diffstat (limited to 'arch')
-rw-r--r--arch/arm/mach-at91/at91sam9g20_reset.S14
1 files changed, 7 insertions, 7 deletions
diff --git a/arch/arm/mach-at91/at91sam9g20_reset.S b/arch/arm/mach-at91/at91sam9g20_reset.S
index f6e9b037f73c..1631c38bc6b8 100644
--- a/arch/arm/mach-at91/at91sam9g20_reset.S
+++ b/arch/arm/mach-at91/at91sam9g20_reset.S
@@ -33,23 +33,23 @@
.globl at91sam9g20_reset
at91sam9g20_reset: mov r0, #0
- mcr p15, 0, r0, c7, c5, 0 @ flush I-cache
+ mcr p15, 0, r0, c7, c5, 0 @ flush I-cache
mrc p15, 0, r0, c1, c0, 0
orr r0, r0, #CP15_CR_I
- mcr p15, 0, r0, c1, c0, 0 @ enable I-cache
+ mcr p15, 0, r0, c1, c0, 0 @ enable I-cache
- ldr r0, =SDRAMC_BASE @ preload constants
+ ldr r0, =SDRAMC_BASE @ preload constants
ldr r1, =RSTC_BASE
mov r2, #1
mov r3, #SDRAMC_LPCB_POWER_DOWN
ldr r4, =RSTC_KEY | RSTC_PERRST | RSTC_PROCRST
- .balign 32 @ align to cache line
+ .balign 32 @ align to cache line
- str r2, [r0, #SDRAMC_TR] @ disable SDRAM access
- str r3, [r0, #SDRAMC_LPR] @ power down SDRAM
- str r4, [r1, #RSTC_CR] @ reset processor
+ str r2, [r0, #SDRAMC_TR] @ disable SDRAM access
+ str r3, [r0, #SDRAMC_LPR] @ power down SDRAM
+ str r4, [r1, #RSTC_CR] @ reset processor
b .

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