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authorTejun Heo <htejun@gmail.com>2005-06-26 23:27:19 +0900
committerJeff Garzik <jgarzik@pobox.com>2005-06-28 00:05:57 -0400
commit62ba2841f2a51848f7cb0499edae3f6803764f2c (patch)
tree8e945184504d0ed608c6e58f092b5c819d1cb098 /drivers/scsi/libata-core.c
parente922256ae4bb6ef954bd7e0740d9753460e0ab72 (diff)
[PATCH] libata: lengthen COMMRESET delay
This patch lengthens the delay between DET setting and clearing for COMMRESET from 400us to 1ms. I couldn't find any requiremen regarding the duration of COMMRESET in SATA I/II specs but AHCI-1.1 10.4.2 states that it should be at least 1ms. Signed-off-by: Tejun Heo <htejun@gmail.com>
Diffstat (limited to 'drivers/scsi/libata-core.c')
-rw-r--r--drivers/scsi/libata-core.c4
1 files changed, 3 insertions, 1 deletions
diff --git a/drivers/scsi/libata-core.c b/drivers/scsi/libata-core.c
index fd66f56fd612..cb535fa185b9 100644
--- a/drivers/scsi/libata-core.c
+++ b/drivers/scsi/libata-core.c
@@ -1408,7 +1408,9 @@ void __sata_phy_reset(struct ata_port *ap)
if (ap->flags & ATA_FLAG_SATA_RESET) {
/* issue phy wake/reset */
scr_write_flush(ap, SCR_CONTROL, 0x301);
- udelay(400); /* FIXME: a guess */
+ /* Couldn't find anything in SATA I/II specs, but
+ * AHCI-1.1 10.4.2 says at least 1 ms. */
+ mdelay(1);
}
scr_write_flush(ap, SCR_CONTROL, 0x300); /* phy wake/clear reset */

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