|author||Chris Wilson <firstname.lastname@example.org>||2018-12-06 08:44:31 +0000|
|committer||Joonas Lahtinen <email@example.com>||2018-12-12 09:06:14 +0200|
drm/i915/execlists: Apply a full mb before execution for Braswell
Braswell is really picky about having our writes posted to memory before we execute or else the GPU may see stale values. A wmb() is insufficient as it only ensures the writes are visible to other cores, we need a full mb() to ensure the writes are in memory and visible to the GPU. The most frequent failure in flushing before execution is that we see stale PTE values and execute the wrong pages. References: 987abd5c62f9 ("drm/i915/execlists: Force write serialisation into context image vs execution") Signed-off-by: Chris Wilson <firstname.lastname@example.org> Cc: Mika Kuoppala <email@example.com> Cc: Tvrtko Ursulin <firstname.lastname@example.org> Cc: Joonas Lahtinen <email@example.com> Cc: firstname.lastname@example.org Reviewed-by: Tvrtko Ursulin <email@example.com> Link: https://firstname.lastname@example.org (cherry picked from commit 490b8c65b9db45896769e1095e78725775f47b3e) Signed-off-by: Joonas Lahtinen <email@example.com>
Diffstat (limited to 'drivers')
1 files changed, 6 insertions, 1 deletions
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 4acb24c90c68..e2cf4f750c66 100644
@@ -442,8 +442,13 @@ static u64 execlists_update_context(struct i915_request *rq)
* may not be visible to the HW prior to the completion of the UC
* register write and that we may begin execution from the context
* before its image is complete leading to invalid PD chasing.
+ * Furthermore, Braswell, at least, wants a full mb to be sure that
+ * the writes are coherent in memory (visible to the GPU) prior to
+ * execution, and not just visible to other CPUs (as is the result of
+ * wmb).