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-rw-r--r--arch/mips/kernel/smp.c25
1 files changed, 4 insertions, 21 deletions
diff --git a/arch/mips/kernel/smp.c b/arch/mips/kernel/smp.c
index 0555fc554f65..c46e479c992b 100644
--- a/arch/mips/kernel/smp.c
+++ b/arch/mips/kernel/smp.c
@@ -51,31 +51,14 @@ int __cpu_logical_map[NR_CPUS]; /* Map logical to physical */
EXPORT_SYMBOL(phys_cpu_present_map);
EXPORT_SYMBOL(cpu_online_map);
+/* This happens early in bootup, can't really do it better */
static void smp_tune_scheduling (void)
{
struct cache_desc *cd = &current_cpu_data.scache;
- unsigned long cachesize; /* kB */
- unsigned long cpu_khz;
+ unsigned long cachesize = cd->linesz * cd->sets * cd->ways;
- /*
- * Crude estimate until we actually meassure ...
- */
- cpu_khz = loops_per_jiffy * 2 * HZ / 1000;
-
- /*
- * Rough estimation for SMP scheduling, this is the number of
- * cycles it takes for a fully memory-limited process to flush
- * the SMP-local cache.
- *
- * (For a P5 this pretty much means we will choose another idle
- * CPU almost always at wakeup time (this is due to the small
- * L1 cache), on PIIs it's around 50-100 usecs, depending on
- * the cache size)
- */
- if (!cpu_khz)
- return;
-
- cachesize = cd->linesz * cd->sets * cd->ways;
+ if (cachesize > max_cache_size)
+ max_cache_size = cachesize;
}
extern void __init calibrate_delay(void);

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