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2018-12-24pwm: imx: Add ipg clock operationAnson Huang1-5/+48
i.MX PWM module's ipg_clk_s is for PWM register access, on most of i.MX SoCs, this ipg_clk_s is from system ipg clock or perclk which is always enabled, but on i.MX7D, the ipg_clk_s is from PWM1_CLK_ROOT which is controlled by CCGR132, that means the CCGR132 MUST be enabled first before accessing PWM registers on i.MX7D. This patch adds ipg clock operation to make sure register access successfully on i.MX7D and it fixes Linux kernel boot up hang during PWM driver probe. Fixes: 4a23e6ee9f69 ("ARM: dts: imx7d-sdb: Restore pwm backlight support") Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
2018-12-24pwm: clps711x: Switch to SPDX identifierAlexander Shiyan1-7/+2
Adopt the SPDX license identifier headers to ease license compliance management. Signed-off-by: Alexander Shiyan <shc_work@mail.ru> Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
2018-12-24pwm: clps711x: Fix period calculationAlexander Shiyan1-2/+2
Commit e39c0df1be5a ("pwm: Introduce the pwm_args concept") has changed the variable for the period for clps711x-pwm driver, so now pwm_get/set_period() works with pwm->state.period variable instead of pwm->args.period. This patch changes the period variable in other places where it is used. Signed-off-by: Alexander Shiyan <shc_work@mail.ru> Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
2018-12-24pwm: bcm2835: Switch to SPDX identifierStefan Wahren1-4/+1
Adopt the SPDX license identifier headers to ease license compliance management. Cc: Bart Tanghe <bart.tanghe@thomasmore.be> Signed-off-by: Stefan Wahren <stefan.wahren@i2se.com> Reviewed-by: Eric Anholt <eric@anholt.net> Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
2018-12-24pwm: Enable Kona PWM to be built for the Cygnus architectureClément Péron1-1/+3
The Cygnus architecture uses a Kona PWM. This is already present in the device tree but can't be built actually. Hence, allow the Kona PWM to be built for the Cygnus architecture. Signed-off-by: Clément Péron <peron.clem@gmail.com> Reviewed-by: Florian Fainelli <f.fainelli@gmail.com> Reviewed-by: Scott Branden <scott.branden@broadcom.com> Acked-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
2018-12-12pwm: imx: Implement get_state() function for hardware readoutMichal Vokáč1-0/+53
Implement the get_state() function and set the initial state to reflect real state of the hardware. This allows to keep the PWM running if it was enabled in bootloader. It is very similar to the GPIO behavior. GPIO pin set as output in bootloader keep the same setting in Linux unless it is reconfigured. If we find the PWM block enabled we need to prepare and enable its source clock otherwise the clock will be disabled late in the boot as unused. That will leave the PWM in enabled state but with disabled clock. That has a side effect that the PWM output is left at its current level at which the clock was disabled. It is totally non-deterministic and it may be LOW or HIGH. Signed-off-by: Michal Vokáč <michal.vokac@ysoft.com> Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
2018-12-12pwm: imx: Use bitops and bitfield macros to define register valuesMichal Vokáč1-20/+58
Use existing macros to define register fields instead of manually shifting the bit masks. Also define some more register bits. Signed-off-by: Michal Vokáč <michal.vokac@ysoft.com> Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
2018-12-12pwm: imx: Sort include filesMichal Vokáč1-6/+6
Sort included header files alphabetically. Signed-off-by: Michal Vokáč <michal.vokac@ysoft.com> Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
2018-11-16pwm: lpc18xx-sct: Don't reconfigure PWM in .request and .freeUwe Kleine-König1-3/+0
Regarding the .request case: The consumer might be interested in taking over the configured state from the boot loader. So the initially configured state should be retained. For the free case the PWM consumer is responsible for disabling the PWM before calling pwm_put() and there are three subcases to consider: a) The PWM is already off. Then there is no gain in disabling the PWM once more. b) The PWM is still running and there is a good reason for that. (Not sure this is a valid case, I cannot imagine such a good reason.) Then it is counterproductive to disable the PWM. c) The PWM is still running because the consumer failed to disable the PWM. Then the consumer needs fixing and there is little incentive to paper over the problem in the backend driver. This aligns the lpc18xx-sct driver to the other PWM drivers that also don't reconfigure the hardware in .request and .free. Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
2018-10-16pwm: lpss: Only set update bit if we are actually changing the settingsHans de Goede1-5/+7
According to the datasheet the update bit must be set if the on-time-div or the base-unit changes. Now that we properly order device resume on Cherry Trail so that the GFX0 _PS0 method no longer exits with an error, we end up with a sequence of events where we are writing the same values twice in a row. First the _PS0 method restores the duty cycle of 0% the GPU driver set on suspend and then the GPU driver first updates just the enabled bit in the pwm_state from 0 to 1, causing us to write the same values again, before restoring the pre-suspend duty-cycle in a separate pwm_apply call. When writing the update bit the second time, without changing any of the values the update bit clears immediately / instantly, instead of staying 1 for a while as usual. After this the next setting of the update bit seems to be ignored, causing the restoring of the pre-suspend duty-cycle to not get applied. This makes the backlight come up with a 0% dutycycle after suspend/resume. Any further brightness changes after this do work. This commit moves the setting of the update bit into pwm_lpss_prepare() and only sets the bit if we have actually changed any of the values. This avoids the setting of the update bit the second time we configure the PWM to 0% dutycycle, this fixes the backlight coming up with 0% duty-cycle after a suspend/resume. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
2018-10-16pwm: lpss: Force runtime-resume on suspend on Cherry TrailHans de Goede2-15/+16
On Cherry Trail devices under Windows the PWM controller used for the backlight is considered part of the GPU even though it is part of the LPSS block and thus is an entirely different independent hardware unit. Because of this on Cherry Trail the GPU's (GFX0 ACPI node) _PS3 and _PS0 methods save and restore the PWM controller registers. If userspace blanks the screen before suspending, such as e.g. GNOME does, then the PWM controller will be runtime-suspended when the suspend starts. This causes the GFX0 _PS? methods to save a value of 0xffffffff for the PWM control register and to restore this value on resume. 0xffffffff is not a valid value for the register and writing this causes problems such as e.g. a flickering backlight. This commit adds a prepare method to the dev_pm_ops and makes it return 0 on Cherry Trail devices forcing a runtime-resume before other device's suspend methods run. This fixes the reading and writing back of 0xffffffff. Since we now always runtime-resume the device on suspend, it will be resumed on resume too and we no longer need to check for the GFX0 _PS0 method having resumed it underneath us, so this commit removes the now no longer necessary complete dev_pm_op. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
2018-10-16pwm: Enable TI ECAP driver for ARCH_K3Vignesh R1-3/+2
K3 devices have the same ECAP IP as OMAP SoCs. Enable driver to be built for K3 devices. Also, drop reference to AM33xx in help text, as IP is found on multiple TI SoCs. Signed-off-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
2018-10-12pwm: Send a uevent on the pwmchip device upon channel sysfs (un)exportFabrice Gasnier1-0/+11
This patch sends a uevent (KOBJ_CHANGE) on the pwmchipN device, everytime a pwmX channel has been exported/unexported via sysfs. This allows udev to implement rules on such events, like: SUBSYSTEM=="pwm*", PROGRAM="/bin/sh -c '\ chown -R root:gpio /sys/class/pwm && chmod -R 770 /sys/class/pwm;\ chown -R root:gpio /sys/devices/platform/soc/*.pwm/pwm/pwmchip* && chmod -R 770 /sys/devices/platform/soc/*.pwm/pwm/pwmchip*\ '" This is a replacement patch for commit 7e5d1fd75c3d ("pwm: Set class for exported channels in sysfs"), see [1]. basic testing: $ udevadm monitor --environment & $ echo 0 > /sys/class/pwm/pwmchip0/export KERNEL[197.321736] change /devices/.../pwm/pwmchip0 (pwm) ACTION=change DEVPATH=/devices/.../pwm/pwmchip0 EXPORT=pwm0 SEQNUM=2045 SUBSYSTEM=pwm [1] https://lkml.org/lkml/2018/9/25/713 Signed-off-by: Fabrice Gasnier <fabrice.gasnier@st.com> Tested-by: Gottfried Haider <gottfried.haider@gmail.com> Tested-by: Michal Vokáč <michal.vokac@ysoft.com> Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
2018-10-12Revert "pwm: Set class for exported channels in sysfs"Fabrice Gasnier1-1/+0
This reverts commit 7e5d1fd75c3dde9fc10c4472b9368089d1b81d00 ("pwm: Set class for exported channels in sysfs") as it causes regression with multiple pwm chip[1], when exporting a pwm channel (echo X > export): - ABI (Documentation/ABI/testing/sysfs-class-pwm) states pwmX should be created in /sys/class/pwm/pwmchipN/pwmX - Reverted patch causes new entry to be also created directly in /sys/class/pwm/pwmX - 1st time, exporting pwmX will create an entry in /sys/class/pwm/pwmX - class attributes are added under pwmX folder, such as export, unexport npwm, symlinks. This is wrong as it belongs to pwmchipN. It may cause bad behavior and report wrong values. - when another export happens on another pwmchip, it can't be created (e.g. -EEXIST). This is causing the issue with multiple pwmchip. Example on stm32 (stm32429i-eval) platform: $ ls /sys/class/pwm pwmchip0 pwmchip4 $ cd /sys/class/pwm/pwmchip0/ $ echo 0 > export $ ls /sys/class/pwm pwm0 pwmchip0 pwmchip4 $ cd /sys/class/pwm/pwmchip4/ $ echo 0 > export sysfs: cannot create duplicate filename '/class/pwm/pwm0' ...Exception stack follows... This is also seen on other platform [2] [1] https://lkml.org/lkml/2018/9/25/713 [2] https://lkml.org/lkml/2018/9/25/447 Signed-off-by: Fabrice Gasnier <fabrice.gasnier@st.com> Tested-by: Gottfried Haider <gottfried.haider@gmail.com> Tested-by: Michal Vokáč <michal.vokac@ysoft.com> Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
2018-10-12pwm: Use SPDX identifier for Renesas driversWolfram Sang2-13/+2
Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Reviewed-by: Simon Horman <horms+renesas@verge.net.au> Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
2018-10-12pwm: lpss: Add get_state callbackHans de Goede1-0/+34
Add a get_state callback so that the initial state correctly reflects the actual hardware state. Cc: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Jani Nikula <jani.nikula@intel.com> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
2018-10-12pwm: lpss: Release runtime-pm reference from the driver's remove callbackHans de Goede1-0/+6
For each pwm output which gets enabled through pwm_lpss_apply(), we do a pm_runtime_get_sync(). This commit adds pm_runtime_put() calls to pwm_lpss_remove() to balance these when the driver gets removed with some of the outputs still enabled. Fixes: f080be27d7d9 ("pwm: lpss: Add support for runtime PM") Acked-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
2018-10-12pwm: lpss: Check PWM powerstate after resume on Cherry Trail devicesHans de Goede2-3/+24
The _PS0 method for the integrated graphics on some Cherry Trail devices (observed on a HP Pavilion X2 10-p0XX) turns on the PWM chip (puts it in D0), causing an inconsistency between the state the pm-core thinks it is in (left runtime suspended as it was before the suspend/resume) and the state it actually is in. Interestingly enough this is done on a device where the pwm controller is not used for the backlight at all, since it uses an eDP panel. On devices where the PWM is used this is not a problem since we will resume it ourselves anyways. This inconsistency causes us to never suspend the pwm controller again, which causes the device to not be able to reach S0ix states when suspended. This commit adds a resume-complete handler, which when we think the device is still run-time suspended checks the actual power-state and if necessary updates the rpm-core's internal state. This fixes the Pavilion X2 10-p0XX not reaching S0ix states when suspended. Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
2018-10-12pwm: lpss: Move struct pwm_lpss_chip definition to the header fileHans de Goede2-10/+8
Move struct pwm_lpss_chip definition from pwm-lpss.c to pwm-lpss.h, so that the pci/platform drivers can access the info member (struct pwm_lpss_boardinfo *). This is a preparation patch for adding platform specific quirks, which the drivers need access to, to pwm_lpss_boardinfo. Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
2018-10-12pwm: lpss: Add ACPI HID for second PWM controller on Cherry Trail devicesHans de Goede1-0/+1
The second PWM controller on Cherry Trail devices uses a separate ACPI HID: "80862289", add this so that the driver will properly bind to the second PWM controller. The second PWM controller is usually not used, the main thing gained by this is properly putting the PWM controller in D3 on suspend. Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
2018-09-26pwm: tegra: Remove gratuituous blank lineThierry Reding1-1/+0
It's common to follow a device tree ID table by the MODULE_DEVICE_TABLE immediately, without an extra blank line between. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
2018-08-20pwm: mediatek: Add MT7628 supportJohn Crispin2-2/+19
Add support for MT7628. The SoC is legacy MIPS and hence has no complex clock tree. This patch add an extra flag to the SoC specific data indicating, that no clocks are present. Signed-off-by: John Crispin <john@phrozen.org> Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com> Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
2018-08-20pwm: meson: Fix mux clock namesJerome Brunet1-2/+1
Current clock name looks like this: /soc/bus@ffd00000/pwm@1b000#mux0 This is bad because CCF uses the clock to create a directory in clk debugfs. With such name, the directory creation (silently) fails and the debugfs entry end up being created at the debugfs root. With this change, the clock name will now be: ffd1b000.pwm#mux0 This matches the clock naming scheme used in the ethernet and mmc driver. It also fixes the problem with debugfs. Fixes: 36af66a79056 ("pwm: Convert to using %pOF instead of full_name") Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Acked-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
2018-08-20pwm: stm32-lp: Remove useless loop in stm32_pwm_lp_remove()Fabrice Gasnier1-3/+1
LPTimer has only one pwm channel (npwm = 1). Remove useless for loop in remove routine. Signed-off-by: Fabrice Gasnier <fabrice.gasnier@st.com> Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
2018-08-20pwm: omap-dmtimer: Return -EPROBE_DEFER if no dmtimer platform dataDavid Rivshin1-2/+3
If a pwm-omap-dmtimer is probed before the dmtimer it uses, the platform data won't be set yet. Fixes: ac30751df953 ("ARM: OMAP: pdata-quirks: Remove unused timer pdata") Cc: <stable@vger.kernel.org> # 4.17+ Signed-off-by: David Rivshin <drivshin@allworx.com> Acked-by: Pavel Machek <pavel@ucw.cz> Tested-by: Pavel Machek <pavel@ucw.cz> Acked-by: Ladislav Michl <ladis@linux-mips.org> Tested-by: Andreas Kemnade <andreas@kemnade.info> Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
2018-07-12pwm: mxs: Switch to SPDX identifierFabio Estevam1-7/+1
Adopt the SPDX license identifier headers to ease license compliance management. Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com> Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
2018-07-09pwm: fsl-ftm: Enable support for the new SoC i.MX8QMshenwei.wang@nxp.com1-0/+5
Enabled the support for the new SoC i.MX8QM by adding the compatible string of "fsl,imx8qm-ftm-pwm" and its per-compatible data with setting "has_enable_bits" to "true". Signed-off-by: Shenwei Wang <shenwei.wang@nxp.com> Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
2018-07-09pwm: fsl-ftm: Added the support of per-compatible datashenwei.wang@nxp.com1-2/+30
On the i.MX8x SoC family, an additional PWM enable bit is added for each PWM channel in the register FTM_SC[23:16]. It supports 8 channels. Bit 16 is for channel 0, and bit 23 is for channel 7. As the IP version information can not be obtained via any of the FTM registers, a property of "has_enable_bits" is added via per-compatible data structure. Signed-off-by: Shenwei Wang <shenwei.wang@nxp.com> Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
2018-07-09pwm: fsl-ftm: Added a dedicated IP interface clockshenwei.wang@nxp.com1-6/+16
The current driver assumes that the ftm_sys clock works as one of the clock sources for the IP block as well as the IP interface clock. This assumption does not apply any more on the latest i.MX8x SoC family. On i.MX8x SoCs, a dedicated IP interface clock is introduced and it must be enabled before accessing any FTM registers. Moreover, the clock can not be used as the source clock for the FTM IP block. This patch introduces the ipg_clk as the dedicated IP interface clock and by default it is the same as the ftm_sys clock if not specified. Signed-off-by: Shenwei Wang <shenwei.wang@nxp.com> Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
2018-07-09pwm: cros-ec: Switch to SPDX identifierEnric Balletbo i Serra1-6/+3
Adopt the SPDX license identifier headers to ease license compliance management. Signed-off-by: Enric Balletbo i Serra <enric.balletbo@collabora.com> Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
2018-07-09pwm: imx: Switch to SPDX identifierFabio Estevam1-4/+1
Adopt the SPDX license identifier headers to ease license compliance management. Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com> Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
2018-07-09pwm: tiehrpwm: Fix disabling of output of PWMsVignesh R1-0/+2
pwm-tiehrpwm driver disables PWM output by putting it in low output state via active AQCSFRC register in ehrpwm_pwm_disable(). But, the AQCSFRC shadow register is not updated. Therefore, when shadow AQCSFRC register is re-enabled in ehrpwm_pwm_enable() (say to enable second PWM output), previous settings are lost as shadow register value is loaded into active register. This results in things like PWMA getting enabled automatically, when PWMB is enabled and vice versa. Fix this by updating AQCSFRC shadow register as well during ehrpwm_pwm_disable(). Fixes: 19891b20e7c2 ("pwm: pwm-tiehrpwm: PWM driver support for EHRPWM") Cc: stable@vger.kernel.org Signed-off-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
2018-07-09pwm: tiehrpwm: Don't use emulation mode bits to control PWM outputVignesh R1-11/+1
As per AM335x TRM SPRUH73P "15.2.2.11 ePWM Behavior During Emulation", TBCTL[15:14] only have effect during emulation suspend events (IOW, to stop PWM when debugging using a debugger). These bits have no effect on PWM output during normal running of system. Hence, remove code accessing these bits as they have no role in enabling/disabling PWMs. Fixes: 19891b20e7c2 ("pwm: pwm-tiehrpwm: PWM driver support for EHRPWM") Cc: stable@vger.kernel.org Signed-off-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
2018-07-09pwm: berlin: Don't use broken prescaler valuesThomas Hebb1-20/+25
The Berlin PWM driver is currently broken on at least BG2CD. The symptoms manifest as a very non-linear and erratic mapping from the duty cycle configured in software to the duty cycle produced by hardware. The cause of the bug is software's configuration of the prescaler, and in particular its usage of the six prescaler values between the minimum value of 1 and the maximum value of 4096. As it turns out, these six values do not actually slow down the PWM clock; rather, they emulate slowing down the clock by internally multiplying the value of TCNT. This would be a fine trick, if not for the fact that the internal, scaled TCNT value has no extra bits beyond the 16 already exposed to software in the register. What this means is that, for a prescaler of 4, the software must ensure that the top two bits of TCNT are not set, because hardware will chop them off; for a prescaler of 8, the top three bits must not be set, and so forth. Software does not currently ensure this, resulting in a TCNT several orders of magnitude lower than intended any time one of those six prescalers are selected. Because hardware chops off the high bits in its internal shift, the middle six prescalers don't actually allow *anything* that the first doesn't. In fact, they are strictly worse than the first, since the internal shift of TCNT prevents software from setting the low bits, decreasing the resolution, without providing any extra high bits. By skipping the useless prescalers entirely, this patch both fixes the driver's behavior and increases its performance (since, when the 4096 prescaler is selected, it now does only a single shift rather than the seven successive divisions it did before). Tested on BG2CD. Signed-off-by: Thomas Hebb <tommyhebb@gmail.com> Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
2018-06-14Merge tag 'pwm/for-4.18-rc1' of ↵Linus Torvalds8-12/+44
git://git.kernel.org/pub/scm/linux/kernel/git/thierry.reding/linux-pwm Pull pwm updates from Thierry Reding: "This contains a couple of fixes and cleanups for the Meson and ACPI/LPSS drivers as well as capture support for STM32. Note that given the cross- subsystem changes, the STM32 patches were merged through the MFD and PWM trees, both sharing an immutable branch" * tag 'pwm/for-4.18-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/thierry.reding/linux-pwm: pwm: stm32: Fix build warning with CONFIG_DMA_ENGINE disabled pwm: stm32: Enforce dependency on CONFIG_MFD_STM32_TIMERS ACPI / LPSS: Add missing prv_offset setting for byt/cht PWM devices pwm: lpss: platform: Save/restore the ctrl register over a suspend/resume dt-bindings: mfd: stm32-timers: Add support for dmas pwm: simplify getting .drvdata pwm: meson: Fix allocation of PWM channel array
2018-06-12treewide: devm_kzalloc() -> devm_kcalloc()Kees Cook1-1/+1
The devm_kzalloc() function has a 2-factor argument form, devm_kcalloc(). This patch replaces cases of: devm_kzalloc(handle, a * b, gfp) with: devm_kcalloc(handle, a * b, gfp) as well as handling cases of: devm_kzalloc(handle, a * b * c, gfp) with: devm_kzalloc(handle, array3_size(a, b, c), gfp) as it's slightly less ugly than: devm_kcalloc(handle, array_size(a, b), c, gfp) This does, however, attempt to ignore constant size factors like: devm_kzalloc(handle, 4 * 1024, gfp) though any constants defined via macros get caught up in the conversion. Any factors with a sizeof() of "unsigned char", "char", and "u8" were dropped, since they're redundant. Some manual whitespace fixes were needed in this patch, as Coccinelle really liked to write "=devm_kcalloc..." instead of "= devm_kcalloc...". The Coccinelle script used for this was: // Fix redundant parens around sizeof(). @@ expression HANDLE; type TYPE; expression THING, E; @@ ( devm_kzalloc(HANDLE, - (sizeof(TYPE)) * E + sizeof(TYPE) * E , ...) | devm_kzalloc(HANDLE, - (sizeof(THING)) * E + sizeof(THING) * E , ...) ) // Drop single-byte sizes and redundant parens. @@ expression HANDLE; expression COUNT; typedef u8; typedef __u8; @@ ( devm_kzalloc(HANDLE, - sizeof(u8) * (COUNT) + COUNT , ...) | devm_kzalloc(HANDLE, - sizeof(__u8) * (COUNT) + COUNT , ...) | devm_kzalloc(HANDLE, - sizeof(char) * (COUNT) + COUNT , ...) | devm_kzalloc(HANDLE, - sizeof(unsigned char) * (COUNT) + COUNT , ...) | devm_kzalloc(HANDLE, - sizeof(u8) * COUNT + COUNT , ...) | devm_kzalloc(HANDLE, - sizeof(__u8) * COUNT + COUNT , ...) | devm_kzalloc(HANDLE, - sizeof(char) * COUNT + COUNT , ...) | devm_kzalloc(HANDLE, - sizeof(unsigned char) * COUNT + COUNT , ...) ) // 2-factor product with sizeof(type/expression) and identifier or constant. @@ expression HANDLE; type TYPE; expression THING; identifier COUNT_ID; constant COUNT_CONST; @@ ( - devm_kzalloc + devm_kcalloc (HANDLE, - sizeof(TYPE) * (COUNT_ID) + COUNT_ID, sizeof(TYPE) , ...) | - devm_kzalloc + devm_kcalloc (HANDLE, - sizeof(TYPE) * COUNT_ID + COUNT_ID, sizeof(TYPE) , ...) | - devm_kzalloc + devm_kcalloc (HANDLE, - sizeof(TYPE) * (COUNT_CONST) + COUNT_CONST, sizeof(TYPE) , ...) | - devm_kzalloc + devm_kcalloc (HANDLE, - sizeof(TYPE) * COUNT_CONST + COUNT_CONST, sizeof(TYPE) , ...) | - devm_kzalloc + devm_kcalloc (HANDLE, - sizeof(THING) * (COUNT_ID) + COUNT_ID, sizeof(THING) , ...) | - devm_kzalloc + devm_kcalloc (HANDLE, - sizeof(THING) * COUNT_ID + COUNT_ID, sizeof(THING) , ...) | - devm_kzalloc + devm_kcalloc (HANDLE, - sizeof(THING) * (COUNT_CONST) + COUNT_CONST, sizeof(THING) , ...) | - devm_kzalloc + devm_kcalloc (HANDLE, - sizeof(THING) * COUNT_CONST + COUNT_CONST, sizeof(THING) , ...) ) // 2-factor product, only identifiers. @@ expression HANDLE; identifier SIZE, COUNT; @@ - devm_kzalloc + devm_kcalloc (HANDLE, - SIZE * COUNT + COUNT, SIZE , ...) // 3-factor product with 1 sizeof(type) or sizeof(expression), with // redundant parens removed. @@ expression HANDLE; expression THING; identifier STRIDE, COUNT; type TYPE; @@ ( devm_kzalloc(HANDLE, - sizeof(TYPE) * (COUNT) * (STRIDE) + array3_size(COUNT, STRIDE, sizeof(TYPE)) , ...) | devm_kzalloc(HANDLE, - sizeof(TYPE) * (COUNT) * STRIDE + array3_size(COUNT, STRIDE, sizeof(TYPE)) , ...) | devm_kzalloc(HANDLE, - sizeof(TYPE) * COUNT * (STRIDE) + array3_size(COUNT, STRIDE, sizeof(TYPE)) , ...) | devm_kzalloc(HANDLE, - sizeof(TYPE) * COUNT * STRIDE + array3_size(COUNT, STRIDE, sizeof(TYPE)) , ...) | devm_kzalloc(HANDLE, - sizeof(THING) * (COUNT) * (STRIDE) + array3_size(COUNT, STRIDE, sizeof(THING)) , ...) | devm_kzalloc(HANDLE, - sizeof(THING) * (COUNT) * STRIDE + array3_size(COUNT, STRIDE, sizeof(THING)) , ...) | devm_kzalloc(HANDLE, - sizeof(THING) * COUNT * (STRIDE) + array3_size(COUNT, STRIDE, sizeof(THING)) , ...) | devm_kzalloc(HANDLE, - sizeof(THING) * COUNT * STRIDE + array3_size(COUNT, STRIDE, sizeof(THING)) , ...) ) // 3-factor product with 2 sizeof(variable), with redundant parens removed. @@ expression HANDLE; expression THING1, THING2; identifier COUNT; type TYPE1, TYPE2; @@ ( devm_kzalloc(HANDLE, - sizeof(TYPE1) * sizeof(TYPE2) * COUNT + array3_size(COUNT, sizeof(TYPE1), sizeof(TYPE2)) , ...) | devm_kzalloc(HANDLE, - sizeof(TYPE1) * sizeof(THING2) * (COUNT) + array3_size(COUNT, sizeof(TYPE1), sizeof(TYPE2)) , ...) | devm_kzalloc(HANDLE, - sizeof(THING1) * sizeof(THING2) * COUNT + array3_size(COUNT, sizeof(THING1), sizeof(THING2)) , ...) | devm_kzalloc(HANDLE, - sizeof(THING1) * sizeof(THING2) * (COUNT) + array3_size(COUNT, sizeof(THING1), sizeof(THING2)) , ...) | devm_kzalloc(HANDLE, - sizeof(TYPE1) * sizeof(THING2) * COUNT + array3_size(COUNT, sizeof(TYPE1), sizeof(THING2)) , ...) | devm_kzalloc(HANDLE, - sizeof(TYPE1) * sizeof(THING2) * (COUNT) + array3_size(COUNT, sizeof(TYPE1), sizeof(THING2)) , ...) ) // 3-factor product, only identifiers, with redundant parens removed. @@ expression HANDLE; identifier STRIDE, SIZE, COUNT; @@ ( devm_kzalloc(HANDLE, - (COUNT) * STRIDE * SIZE + array3_size(COUNT, STRIDE, SIZE) , ...) | devm_kzalloc(HANDLE, - COUNT * (STRIDE) * SIZE + array3_size(COUNT, STRIDE, SIZE) , ...) | devm_kzalloc(HANDLE, - COUNT * STRIDE * (SIZE) + array3_size(COUNT, STRIDE, SIZE) , ...) | devm_kzalloc(HANDLE, - (COUNT) * (STRIDE) * SIZE + array3_size(COUNT, STRIDE, SIZE) , ...) | devm_kzalloc(HANDLE, - COUNT * (STRIDE) * (SIZE) + array3_size(COUNT, STRIDE, SIZE) , ...) | devm_kzalloc(HANDLE, - (COUNT) * STRIDE * (SIZE) + array3_size(COUNT, STRIDE, SIZE) , ...) | devm_kzalloc(HANDLE, - (COUNT) * (STRIDE) * (SIZE) + array3_size(COUNT, STRIDE, SIZE) , ...) | devm_kzalloc(HANDLE, - COUNT * STRIDE * SIZE + array3_size(COUNT, STRIDE, SIZE) , ...) ) // Any remaining multi-factor products, first at least 3-factor products, // when they're not all constants... @@ expression HANDLE; expression E1, E2, E3; constant C1, C2, C3; @@ ( devm_kzalloc(HANDLE, C1 * C2 * C3, ...) | devm_kzalloc(HANDLE, - (E1) * E2 * E3 + array3_size(E1, E2, E3) , ...) | devm_kzalloc(HANDLE, - (E1) * (E2) * E3 + array3_size(E1, E2, E3) , ...) | devm_kzalloc(HANDLE, - (E1) * (E2) * (E3) + array3_size(E1, E2, E3) , ...) | devm_kzalloc(HANDLE, - E1 * E2 * E3 + array3_size(E1, E2, E3) , ...) ) // And then all remaining 2 factors products when they're not all constants, // keeping sizeof() as the second factor argument. @@ expression HANDLE; expression THING, E1, E2; type TYPE; constant C1, C2, C3; @@ ( devm_kzalloc(HANDLE, sizeof(THING) * C2, ...) | devm_kzalloc(HANDLE, sizeof(TYPE) * C2, ...) | devm_kzalloc(HANDLE, C1 * C2 * C3, ...) | devm_kzalloc(HANDLE, C1 * C2, ...) | - devm_kzalloc + devm_kcalloc (HANDLE, - sizeof(TYPE) * (E2) + E2, sizeof(TYPE) , ...) | - devm_kzalloc + devm_kcalloc (HANDLE, - sizeof(TYPE) * E2 + E2, sizeof(TYPE) , ...) | - devm_kzalloc + devm_kcalloc (HANDLE, - sizeof(THING) * (E2) + E2, sizeof(THING) , ...) | - devm_kzalloc + devm_kcalloc (HANDLE, - sizeof(THING) * E2 + E2, sizeof(THING) , ...) | - devm_kzalloc + devm_kcalloc (HANDLE, - (E1) * E2 + E1, E2 , ...) | - devm_kzalloc + devm_kcalloc (HANDLE, - (E1) * (E2) + E1, E2 , ...) | - devm_kzalloc + devm_kcalloc (HANDLE, - E1 * E2 + E1, E2 , ...) ) Signed-off-by: Kees Cook <keescook@chromium.org>
2018-06-06pwm: stm32: Fix build warning with CONFIG_DMA_ENGINE disabledArnd Bergmann1-3/+1
Without dmaengine support, we get a harmless warning about an unused function: drivers/pwm/pwm-stm32.c:166:12: error: 'stm32_pwm_capture' defined but not used [-Werror=unused-function] Changing the #ifdef to an IS_ENABLED() check shuts up that warning and is slightly nicer to read. Fixes: 53e38fe73f94 ("pwm: stm32: Add capture support") Signed-off-by: Arnd Bergmann <arnd@arndb.de> Acked-by: Fabrice Gasnier <fabrice.gasnier@st.com> Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
2018-06-06Merge tag 'ib-mfd-pwm-v4.18-1' of ↵Thierry Reding1-0/+257
git://git.kernel.org/pub/scm/linux/kernel/git/lee/mfd into for-next Immutable branch between MFD and PWM due for the v4.18 merge window (v2)
2018-06-06pwm: stm32: Enforce dependency on CONFIG_MFD_STM32_TIMERSArnd Bergmann1-1/+1
When compile-testing the PWM driver without also enabling the stm32_timers MFD, we run into a link error: drivers/pwm/pwm-stm32.o: In function `stm32_pwm_raw_capture.isra.6': pwm-stm32.c:(.text+0xcb0): undefined reference to `stm32_timers_dma_burst_read' We don't need the '|| COMPILE_TEST' here, since stm32_timers itself can be built with CONFIG_COMPILE_TEST on all architectures, so we do get the coverage through allmodconfig and randconfig builds even when we make it a hard dependency. Fixes: 7edf7369205b ("pwm: Add driver for STM32 plaftorm") Signed-off-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
2018-06-06pwm: lpss: platform: Save/restore the ctrl register over a suspend/resumeHans de Goede3-0/+37
On some devices the contents of the ctrl register get lost over a suspend/resume and the PWM comes back up disabled after the resume. This is seen on some Bay Trail devices with the PWM in ACPI enumerated mode, so it shows up as a platform device instead of a PCI device. If we still think it is enabled and then try to change the duty-cycle after this, we end up with a "PWM_SW_UPDATE was not cleared" error and the PWM is stuck in that state from then on. This commit adds suspend and resume pm callbacks to the pwm-lpss-platform code, which save/restore the ctrl register over a suspend/resume, fixing this. Note that: 1) There is no need to do this over a runtime suspend, since we only runtime suspend when disabled and then we properly set the enable bit and reprogram the timings when we re-enable the PWM. 2) This may be happening on more systems then we realize, but has been covered up sofar by a bug in the acpi-lpss.c code which was save/restoring the regular device registers instead of the lpss private registers due to lpss_device_desc.prv_offset not being set. This is fixed by a later patch in this series. Cc: stable@vger.kernel.org Signed-off-by: Hans de Goede <hdegoede@redhat.com> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
2018-06-04pwm: stm32: Initialize raw local variablesFabrice Gasnier1-1/+1
This removes build warning when COMPILE_TEST=y and MFD_STM32_TIMERS=n in drivers/pwm/pwm-stm32.c. In function 'stm32_pwm_capture' 'raw_prd' and 'raw_dty' may be used uninitialized in this function [-Wmaybe-uninitialized] Signed-off-by: Fabrice Gasnier <fabrice.gasnier@st.com> Acked-by: Thierry Reding <thierry.reding@gmail.com> Tested-by: Randy Dunlap <rdunlap@infradead.org> Signed-off-by: Lee Jones <lee.jones@linaro.org>
2018-05-16pwm: stm32: Use input prescaler to improve period captureFabrice Gasnier1-2/+61
Using input prescaler, capture unit will trigger DMA once every configurable /2, /4 or /8 events (rising edge). This helps improve period (only) capture accuracy at high rates. Signed-off-by: Fabrice Gasnier <fabrice.gasnier@st.com> Reviewed-by: Benjamin Gaignard <benjamin.gaignard@linaro.org> Acked-by: Thierry Reding <thierry.reding@gmail.com> Signed-off-by: Lee Jones <lee.jones@linaro.org>
2018-05-16pwm: stm32: Improve capture by tuning counter prescalerFabrice Gasnier1-1/+23
Currently, capture is based on timeout window to configure prescaler. PWM capture framework provides 1s window at the time of writing. There's place for improvement, after input signal has been captured once: - Finer tune counter clock prescaler, by using 1st capture result (with arbitrary margin). - Do a 2nd capture, with scaled capture window. This increases accuracy, especially at high rates. Signed-off-by: Fabrice Gasnier <fabrice.gasnier@st.com> Reviewed-by: Benjamin Gaignard <benjamin.gaignard@linaro.org> Acked-by: Thierry Reding <thierry.reding@gmail.com> Signed-off-by: Lee Jones <lee.jones@linaro.org>
2018-05-16pwm: stm32: Add capture supportFabrice Gasnier1-0/+176
Add support for PMW input mode on pwm-stm32. STM32 timers support period and duty cycle capture as long as they have at least two PWM channels. One capture channel is used for period (rising-edge), one for duty-cycle (falling-edge). When there's only one channel available, only period can be captured. Duty-cycle is simply zero'ed in such a case. Capture requires exclusive access (e.g. no pwm output running at the same time, to protect common prescaler). Timer DMA burst mode (from MFD core) is being used, to take two snapshots of capture registers (upon each period rising edge). Signed-off-by: Fabrice Gasnier <fabrice.gasnier@st.com> Reviewed-by: Benjamin Gaignard <benjamin.gaignard@linaro.org> Acked-by: Thierry Reding <thierry.reding@gmail.com> Signed-off-by: Lee Jones <lee.jones@linaro.org>
2018-04-30pwm: simplify getting .drvdataWolfram Sang2-6/+3
We should get drvdata from struct device directly. Going via platform_device is an unneeded step back and forth. Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com> Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
2018-04-30pwm: meson: Fix allocation of PWM channel arrayMartin Blumenstingl1-2/+2
Using the pwm-meson driver on the 32-bit SoCs causes memory corruption. The result are some hard-to-explain errors, for example devm_clk_register() crashes with a NULL dereference somewhere deep in the common clock framework code. In some cases the kernel even refused to boot when any of the PWM controllers were enabled on Meson8b. The root cause is an incorrect memory size in the devm_kcalloc() call in meson_pwm_probe(). The code allocates an array of meson_pwm_channel structs, but the size given is the size of the meson_pwm struct (which seems like a small copy-and-paste error, as meson_pwm is allocated a few lines above). Even with this typo the code seemed to work fine on the 64-bit GX SoCs (maybe due to the structs having the same size in the compiled result, but I haven't checked this further). Fixes: 211ed630753d2f ("pwm: Add support for Meson PWM Controller") Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
2018-04-13Merge tag 'pwm/for-4.17-rc1' of ↵Linus Torvalds11-56/+161
git://git.kernel.org/pub/scm/linux/kernel/git/thierry.reding/linux-pwm Pull pwm updates from Thierry Reding: "This set of changes adds support for more generations of the RCar controller as well as runtime PM support. The JZ4740 driver gains support for device tree and can now be used on all Ingenic SoCs. Rounding things off is a random assortment of fixes and cleanups all across the board" * tag 'pwm/for-4.17-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/thierry.reding/linux-pwm: (29 commits) pwm: rcar: Add suspend/resume support pwm: rcar: Use PM Runtime to control module clock dt-bindings: pwm: rcar: Add bindings for R-Car M3N support pwm: rcar: Fix a condition to prevent mismatch value setting to duty pwm: sysfs: Use put_device() instead of kfree() dt-bindings: pwm: sunxi: Add new compatible strings pwm: sun4i: Simplify controller mapping pwm: sun4i: Drop unused .has_rdy member pwm: sun4i: Properly check current state pwm: Remove depends on AVR32 pwm: stm32: LPTimer: Use 3 cells ->of_xlate() dt-bindings: pwm-stm32-lp: Add #pwm-cells pwm: stm32: Protect common prescaler for all channels pwm: stm32: Remove unused struct device pwm: mediatek: Improve precision in rate calculation pwm: mediatek: Remove redundant MODULE_ALIAS entries pwm: mediatek: Fix up PWM4 and PWM5 malfunction on MT7623 pwm: jz4740: Enable for all Ingenic SoCs pwm: jz4740: Add support for devicetree pwm: jz4740: Implement ->set_polarity() ...
2018-04-06Merge tag 'armsoc-soc' of ↵Linus Torvalds1-26/+42
git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc Pull ARM SoC platform updates from Arnd Bergmann: "This release brings up a new platform based on the old ARM9 core: the Nuvoton NPCM is used as a baseboard management controller, competing with the better known ASpeed AST2xx series. Another important change is the addition of ARMv7-A based chips in mach-stm32. The older parts in this platform are ARMv7-M based microcontrollers, now they are expanding to general-purpose workloads. The other changes are the usual defconfig updates to enable additional drivers, lesser bugfixes. The largest updates as often are the ongoing OMAP cleanups, but we also have a number of changes for the older PXA and davinci platforms this time. For the Renesas shmobile/r-car platform, some new infrastructure is needed to make the watchdog work correctly. Supporting Multiprocessing on Allwinner A80 required a significant amount of new code, but is not doing anything unexpected" * tag 'armsoc-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (179 commits) arm: npcm: modify configuration for the NPCM7xx BMC. MAINTAINERS: update entry for ARM/berlin ARM: omap2: fix am43xx build without L2X0 ARM: davinci: da8xx: simplify CFGCHIP regmap_config ARM: davinci: da8xx: fix oops in USB PHY driver due to stack allocated platform_data ARM: multi_v7_defconfig: add NXP FlexCAN IP support ARM: multi_v7_defconfig: enable thermal driver for i.MX devices ARM: multi_v7_defconfig: add RN5T618 PMIC family support ARM: multi_v7_defconfig: add NXP graphics drivers ARM: multi_v7_defconfig: add GPMI NAND controller support ARM: multi_v7_defconfig: add OCOTP driver for NXP SoCs ARM: multi_v7_defconfig: configure I2C driver built-in arm64: defconfig: add CONFIG_UNIPHIER_THERMAL and CONFIG_SNI_AVE ARM: imx: fix imx6sll-only build ARM: imx: select ARM_CPU_SUSPEND for CPU_IDLE as well ARM: mxs_defconfig: Re-sync defconfig ARM: imx_v4_v5_defconfig: Use the generic fsl-asoc-card driver ARM: imx_v4_v5_defconfig: Re-sync defconfig arm64: defconfig: enable stmmac ethernet to defconfig ARM: EXYNOS: Simplify code in coupled CPU idle hot path ...
2018-03-27pwm: rcar: Add suspend/resume supportYoshihiro Shimoda1-0/+42
This patch adds suspend/resume support for Renesas PWM driver. Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
2018-03-27pwm: rcar: Use PM Runtime to control module clockHien Dang1-6/+2
Runtime PM API (pm_runtime_get_sync/pm_runtime_put) should be used to control module clock instead of clk_prepare_enable and clk_disable_unprepare. Signed-off-by: Hien Dang <hien.dang.eb@renesas.com> Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Thierry Reding <thierry.reding@gmail.com>

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