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authorMarkus Stockhausen <stockhausen@collogia.de>2015-01-30 15:39:23 +0100
committerHerbert Xu <herbert@gondor.apana.org.au>2015-02-27 22:48:45 +1300
commit6bb71004aa84054058baf4e8a58a53c4e29e5b9c (patch)
tree69027561ee3ac5cb77b9bd7624c6f8ad06237105 /crypto
parentc517d838eb7d07bbe9507871fab3931deccff539 (diff)
crypto: ppc/sha256 - assembler
This is the assembler code for SHA256 implementation with the SIMD SPE instruction set. Although being only a 32 bit architecture GPRs are extended to 64 bit presenting two 32 bit values. With the enhanced instruction set we can operate on them in parallel. That helps reducing the time to calculate W16-W64. For increasing performance even more the assembler function can compute hashes for more than one 64 byte input block. That saves a lot of register saving/restoring The state of the used SPE registers is preserved via the stack so we can run from interrupt context. There might be the case that we interrupt ourselves and push sensitive data from another context onto our stack. Clear this area in the stack afterwards to avoid information leakage. The code is endian independant. Signed-off-by: Markus Stockhausen <stockhausen@collogia.de> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
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