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authorLinus Torvalds <torvalds@linux-foundation.org>2012-08-17 08:10:12 -0700
committerLinus Torvalds <torvalds@linux-foundation.org>2012-08-17 08:10:12 -0700
commit9d0f8140fc8a723af4eb1ec4d757847515649574 (patch)
tree37d8ca17ea77fd6847f3ea06391665fa80f70ea0 /arch/c6x
parentef824bfba2cce6a75c7cd740f6ad80581e75a109 (diff)
parent01ddd9a809b9a95df097ff1b5565f806e681a606 (diff)
Merge tag 'for-linus' of git://linux-c6x.org/git/projects/linux-c6x-upstreaming
Pull C6X atomic64 support from Mark Salter: "Enable atomic64 ops in C6X - define L1_CACHE_SHIFT - select GENERIC_ATOMIC64" * tag 'for-linus' of git://linux-c6x.org/git/projects/linux-c6x-upstreaming: C6X: select GENERIC_ATOMIC64 C6X: add Lx_CACHE_SHIFT defines
Diffstat (limited to 'arch/c6x')
-rw-r--r--arch/c6x/Kconfig1
-rw-r--r--arch/c6x/include/asm/cache.h16
2 files changed, 12 insertions, 5 deletions
diff --git a/arch/c6x/Kconfig b/arch/c6x/Kconfig
index 052f81a76239..983c859e40b7 100644
--- a/arch/c6x/Kconfig
+++ b/arch/c6x/Kconfig
@@ -6,6 +6,7 @@
config C6X
def_bool y
select CLKDEV_LOOKUP
+ select GENERIC_ATOMIC64
select GENERIC_IRQ_SHOW
select HAVE_ARCH_TRACEHOOK
select HAVE_DMA_API_DEBUG
diff --git a/arch/c6x/include/asm/cache.h b/arch/c6x/include/asm/cache.h
index 6d521d96d941..09c5a0f5f4d1 100644
--- a/arch/c6x/include/asm/cache.h
+++ b/arch/c6x/include/asm/cache.h
@@ -1,7 +1,7 @@
/*
* Port on Texas Instruments TMS320C6x architecture
*
- * Copyright (C) 2005, 2006, 2009, 2010 Texas Instruments Incorporated
+ * Copyright (C) 2005, 2006, 2009, 2010, 2012 Texas Instruments Incorporated
* Author: Aurelien Jacquiot (aurelien.jacquiot@jaluna.com)
*
* This program is free software; you can redistribute it and/or modify
@@ -16,9 +16,14 @@
/*
* Cache line size
*/
-#define L1D_CACHE_BYTES 64
-#define L1P_CACHE_BYTES 32
-#define L2_CACHE_BYTES 128
+#define L1D_CACHE_SHIFT 6
+#define L1D_CACHE_BYTES (1 << L1D_CACHE_SHIFT)
+
+#define L1P_CACHE_SHIFT 5
+#define L1P_CACHE_BYTES (1 << L1P_CACHE_SHIFT)
+
+#define L2_CACHE_SHIFT 7
+#define L2_CACHE_BYTES (1 << L2_CACHE_SHIFT)
/*
* L2 used as cache
@@ -29,7 +34,8 @@
* For practical reasons the L1_CACHE_BYTES defines should not be smaller than
* the L2 line size
*/
-#define L1_CACHE_BYTES L2_CACHE_BYTES
+#define L1_CACHE_SHIFT L2_CACHE_SHIFT
+#define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT)
#define L2_CACHE_ALIGN_LOW(x) \
(((x) & ~(L2_CACHE_BYTES - 1)))

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