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authorLeonid Yegoshin <Leonid.Yegoshin@imgtec.com>2013-11-14 16:12:23 +0000
committerRalf Baechle <ralf@linux-mips.org>2014-01-22 20:18:58 +0100
commit1745c1ef88c095a99c95d13b275774d18774465d (patch)
tree9ea07338f8852f3a6db815e8ce945023c99248ad /arch/mips/kernel
parentc01905eeee579db98dd6b39d3f41497065ecc273 (diff)
MIPS: features: Add initial support for TLBINVF capable cores
New Aptiv cores support the TLBINVF instruction for flushing the VTLB. Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com> Signed-off-by: Markos Chandras <markos.chandras@imgtec.com> Signed-off-by: John Crispin <blogic@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/6130/
Diffstat (limited to 'arch/mips/kernel')
-rw-r--r--arch/mips/kernel/cpu-probe.c5
1 files changed, 5 insertions, 0 deletions
diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c
index e2b2d2043701..a284e8cb8c28 100644
--- a/arch/mips/kernel/cpu-probe.c
+++ b/arch/mips/kernel/cpu-probe.c
@@ -286,6 +286,11 @@ static inline unsigned int decode_config4(struct cpuinfo_mips *c)
&& cpu_has_tlb)
c->tlbsize += (config4 & MIPS_CONF4_MMUSIZEEXT) * 0x40;
+ if (cpu_has_tlb) {
+ if (((config4 & MIPS_CONF4_IE) >> 29) == 2)
+ c->options |= MIPS_CPU_TLBINV;
+ }
+
c->kscratch_mask = (config4 >> 16) & 0xff;
return config4 & MIPS_CONF_M;

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