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authorSteven J. Hill <Steven.Hill@imgtec.com>2013-11-14 16:12:24 +0000
committerRalf Baechle <ralf@linux-mips.org>2014-01-22 20:18:58 +0100
commit4a0156fbfb78b8006ce9b2ffac9383b7d4a8192b (patch)
tree316ae10e4705f42a0690d44254be218c4bedbc03 /arch/mips/kernel
parent1745c1ef88c095a99c95d13b275774d18774465d (diff)
MIPS: features: Add initial support for Segmentation Control registers
MIPS32R3 introduced a new set of Segmentation Control registers which increase the flexibility of the segmented-based memory scheme. Signed-off-by: Steven J. Hill <Steven.Hill@imgtec.com> Signed-off-by: Markos Chandras <markos.chandras@imgtec.com> Signed-off-by: John Crispin <blogic@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/6131/
Diffstat (limited to 'arch/mips/kernel')
-rw-r--r--arch/mips/kernel/cpu-probe.c2
1 files changed, 2 insertions, 0 deletions
diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c
index a284e8cb8c28..e1acfa81a053 100644
--- a/arch/mips/kernel/cpu-probe.c
+++ b/arch/mips/kernel/cpu-probe.c
@@ -272,6 +272,8 @@ static inline unsigned int decode_config3(struct cpuinfo_mips *c)
c->options |= MIPS_CPU_MICROMIPS;
if (config3 & MIPS_CONF3_VZ)
c->ases |= MIPS_ASE_VZ;
+ if (config3 & MIPS_CONF3_SC)
+ c->options |= MIPS_CPU_SEGMENTS;
return config3 & MIPS_CONF_M;
}

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