path: root/arch/powerpc/include/asm/kvm_book3s_asm.h
diff options
authorPaul Mackerras <paulus@samba.org>2013-09-20 14:52:39 +1000
committerAlexander Graf <agraf@suse.de>2013-10-17 14:45:02 +0200
commit4b8473c9c19dff1b0c672f182cc50b9952cf42e7 (patch)
treec4e91c0612665859589f0cf12d32eff6c8af4990 /arch/powerpc/include/asm/kvm_book3s_asm.h
parenta0144e2a6b0b4a137a32f0102354782547bf0935 (diff)
KVM: PPC: Book3S HV: Add support for guest Program Priority Register
POWER7 and later IBM server processors have a register called the Program Priority Register (PPR), which controls the priority of each hardware CPU SMT thread, and affects how fast it runs compared to other SMT threads. This priority can be controlled by writing to the PPR or by use of a set of instructions of the form or rN,rN,rN which are otherwise no-ops but have been defined to set the priority to particular levels. This adds code to context switch the PPR when entering and exiting guests and to make the PPR value accessible through the SET/GET_ONE_REG interface. When entering the guest, we set the PPR as late as possible, because if we are setting a low thread priority it will make the code run slowly from that point on. Similarly, the first-level interrupt handlers save the PPR value in the PACA very early on, and set the thread priority to the medium level, so that the interrupt handling code runs at a reasonable speed. Acked-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Paul Mackerras <paulus@samba.org> Signed-off-by: Alexander Graf <agraf@suse.de>
Diffstat (limited to 'arch/powerpc/include/asm/kvm_book3s_asm.h')
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/powerpc/include/asm/kvm_book3s_asm.h b/arch/powerpc/include/asm/kvm_book3s_asm.h
index 9039d3c97eec..22f46061ae84 100644
--- a/arch/powerpc/include/asm/kvm_book3s_asm.h
+++ b/arch/powerpc/include/asm/kvm_book3s_asm.h
@@ -101,6 +101,7 @@ struct kvmppc_host_state {
u64 cfar;
+ u64 ppr;

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