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authorCatalin Udma <catalin.udma@freescale.com>2013-06-05 20:22:08 (GMT)
committerScott Wood <scottwood@freescale.com>2013-08-07 23:38:03 (GMT)
commit96c3c9e78f7fe45303985cce13ce26e35afd01ba (patch)
tree96f0e95f0472e909dde39b3e1afe505a53398d2e /arch/powerpc/perf
parenta9a5cda06922545ed7540cf5ed7e5ad6b80851d9 (diff)
powerpc/perf: increase the perf HW events to 6
This change is required after the e6500 perf support has been added. There are 6 counters in e6500 core instead of 4 in e500 core and the MAX_HWEVENTS counter should be changed accordingly from 4 to 6. Added also runtime check for counters overflow. Signed-off-by: Catalin Udma <catalin.udma@freescale.com> Signed-off-by: Lijun Pan <Lijun.Pan@freescale.com> Signed-off-by: Scott Wood <scottwood@freescale.com>
Diffstat (limited to 'arch/powerpc/perf')
-rw-r--r--arch/powerpc/perf/core-fsl-emb.c6
1 files changed, 6 insertions, 0 deletions
diff --git a/arch/powerpc/perf/core-fsl-emb.c b/arch/powerpc/perf/core-fsl-emb.c
index 106c533..0b13f74 100644
--- a/arch/powerpc/perf/core-fsl-emb.c
+++ b/arch/powerpc/perf/core-fsl-emb.c
@@ -462,6 +462,12 @@ static int fsl_emb_pmu_event_init(struct perf_event *event)
int num_restricted;
int i;
+ if (ppmu->n_counter > MAX_HWEVENTS) {
+ WARN(1, "No. of perf counters (%d) is higher than max array size(%d)\n",
+ ppmu->n_counter, MAX_HWEVENTS);
+ ppmu->n_counter = MAX_HWEVENTS;
+ }
+
switch (event->attr.type) {
case PERF_TYPE_HARDWARE:
ev = event->attr.config;

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