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authorSylwester Nawrocki <s.nawrocki@samsung.com>2012-09-17 06:03:38 -0300
committerMauro Carvalho Chehab <mchehab@redhat.com>2012-10-05 22:35:16 -0300
commit65214a8603e3ec3b1c2bc4104e6806e7cf6d23ed (patch)
tree21b2b2607f1663a571ba13f0054e6a445b53f43e /drivers/media/platform/s5p-fimc/mipi-csis.c
parent09ff034047cb3846090215358f20e0e94c60b901 (diff)
[media] s5p-csis: Allow to specify pixel clock's source through platform data
Depending on the sensor configuration it might be required to adjust the CSIS's output pixel clock so it is greater than its input pixel clock, in order to avoid the input data FIFO overflow. Use platform data to select SCLK_CSIS clock from CMU as a source, rather than CSI APB clock. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
Diffstat (limited to 'drivers/media/platform/s5p-fimc/mipi-csis.c')
-rw-r--r--drivers/media/platform/s5p-fimc/mipi-csis.c4
1 files changed, 3 insertions, 1 deletions
diff --git a/drivers/media/platform/s5p-fimc/mipi-csis.c b/drivers/media/platform/s5p-fimc/mipi-csis.c
index 983e81f08cd6..4c961b1b68e6 100644
--- a/drivers/media/platform/s5p-fimc/mipi-csis.c
+++ b/drivers/media/platform/s5p-fimc/mipi-csis.c
@@ -322,8 +322,10 @@ static void s5pcsis_set_params(struct csis_state *state)
val |= S5PCSIS_CTRL_ALIGN_32BIT;
else /* 24-bits */
val &= ~S5PCSIS_CTRL_ALIGN_32BIT;
- /* Not using external clock. */
+
val &= ~S5PCSIS_CTRL_WCLK_EXTCLK;
+ if (pdata->wclk_source)
+ val |= S5PCSIS_CTRL_WCLK_EXTCLK;
s5pcsis_write(state, S5PCSIS_CTRL, val);
/* Update the shadow register. */

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