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authorArchit Taneja <archit@ti.com>2011-05-06 11:45:50 +0530
committerTomi Valkeinen <tomi.valkeinen@ti.com>2011-05-11 14:20:52 +0300
commit702d144845086cacf8bb4f23196189f260c250e2 (patch)
tree536f9af661ea3cd004591c3bde278febf0d3d786 /drivers/video/omap2/dss/dispc.h
parent9b372c2d9da43be00e8a267730a2428e0eae12e8 (diff)
OMAP: DSS2: Clean up DISPC overlay manager register definitions
Represent manager/channel specific DISPC registers as inline functions returning the required dispc_reg struct. This is done since the current method is not scalable as the number of overlay managers increase in number. Signed-off-by: Archit Taneja <archit@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
Diffstat (limited to 'drivers/video/omap2/dss/dispc.h')
-rw-r--r--drivers/video/omap2/dss/dispc.h212
1 files changed, 187 insertions, 25 deletions
diff --git a/drivers/video/omap2/dss/dispc.h b/drivers/video/omap2/dss/dispc.h
index f22346b59c58..05e56621d1f4 100644
--- a/drivers/video/omap2/dss/dispc.h
+++ b/drivers/video/omap2/dss/dispc.h
@@ -25,42 +25,20 @@ struct dispc_reg { u16 idx; };
#define DISPC_REG(idx) ((const struct dispc_reg) { idx })
-/*
- * DISPC common registers and
- * DISPC channel registers , ch = 0 for LCD, ch = 1 for
- * DIGIT, and ch = 2 for LCD2
- */
+/* DISPC common registers */
#define DISPC_REVISION DISPC_REG(0x0000)
#define DISPC_SYSCONFIG DISPC_REG(0x0010)
#define DISPC_SYSSTATUS DISPC_REG(0x0014)
#define DISPC_IRQSTATUS DISPC_REG(0x0018)
#define DISPC_IRQENABLE DISPC_REG(0x001C)
#define DISPC_CONTROL DISPC_REG(0x0040)
-#define DISPC_CONTROL2 DISPC_REG(0x0238)
#define DISPC_CONFIG DISPC_REG(0x0044)
-#define DISPC_CONFIG2 DISPC_REG(0x0620)
#define DISPC_CAPABLE DISPC_REG(0x0048)
-#define DISPC_DEFAULT_COLOR(ch) DISPC_REG(ch == 0 ? 0x004C : \
- (ch == 1 ? 0x0050 : 0x03AC))
-#define DISPC_TRANS_COLOR(ch) DISPC_REG(ch == 0 ? 0x0054 : \
- (ch == 1 ? 0x0058 : 0x03B0))
#define DISPC_LINE_STATUS DISPC_REG(0x005C)
#define DISPC_LINE_NUMBER DISPC_REG(0x0060)
-#define DISPC_TIMING_H(ch) DISPC_REG(ch != 2 ? 0x0064 : 0x0400)
-#define DISPC_TIMING_V(ch) DISPC_REG(ch != 2 ? 0x0068 : 0x0404)
-#define DISPC_POL_FREQ(ch) DISPC_REG(ch != 2 ? 0x006C : 0x0408)
-#define DISPC_DIVISORo(ch) DISPC_REG(ch != 2 ? 0x0070 : 0x040C)
#define DISPC_GLOBAL_ALPHA DISPC_REG(0x0074)
-#define DISPC_SIZE_DIG DISPC_REG(0x0078)
-#define DISPC_SIZE_LCD(ch) DISPC_REG(ch != 2 ? 0x007C : 0x03CC)
-
-#define DISPC_DATA_CYCLE1(ch) DISPC_REG(ch != 2 ? 0x01D4 : 0x03C0)
-#define DISPC_DATA_CYCLE2(ch) DISPC_REG(ch != 2 ? 0x01D8 : 0x03C4)
-#define DISPC_DATA_CYCLE3(ch) DISPC_REG(ch != 2 ? 0x01DC : 0x03C8)
-#define DISPC_CPR_COEF_R(ch) DISPC_REG(ch != 2 ? 0x0220 : 0x03BC)
-#define DISPC_CPR_COEF_G(ch) DISPC_REG(ch != 2 ? 0x0224 : 0x03B8)
-#define DISPC_CPR_COEF_B(ch) DISPC_REG(ch != 2 ? 0x0228 : 0x03B4)
-
+#define DISPC_CONTROL2 DISPC_REG(0x0238)
+#define DISPC_CONFIG2 DISPC_REG(0x0620)
#define DISPC_DIVISOR DISPC_REG(0x0804)
/* DISPC overlay registers */
@@ -105,6 +83,190 @@ struct dispc_reg { u16 idx; };
#define DISPC_OVL_PRELOAD(n) DISPC_REG(DISPC_OVL_BASE(n) + \
DISPC_PRELOAD_OFFSET(n))
+/* DISPC manager/channel specific registers */
+static inline struct dispc_reg DISPC_DEFAULT_COLOR(enum omap_channel channel)
+{
+ switch (channel) {
+ case OMAP_DSS_CHANNEL_LCD:
+ return DISPC_REG(0x004C);
+ case OMAP_DSS_CHANNEL_DIGIT:
+ return DISPC_REG(0x0050);
+ case OMAP_DSS_CHANNEL_LCD2:
+ return DISPC_REG(0x03AC);
+ default:
+ BUG();
+ }
+}
+
+static inline struct dispc_reg DISPC_TRANS_COLOR(enum omap_channel channel)
+{
+ switch (channel) {
+ case OMAP_DSS_CHANNEL_LCD:
+ return DISPC_REG(0x0054);
+ case OMAP_DSS_CHANNEL_DIGIT:
+ return DISPC_REG(0x0058);
+ case OMAP_DSS_CHANNEL_LCD2:
+ return DISPC_REG(0x03B0);
+ default:
+ BUG();
+ }
+}
+
+static inline struct dispc_reg DISPC_TIMING_H(enum omap_channel channel)
+{
+ switch (channel) {
+ case OMAP_DSS_CHANNEL_LCD:
+ return DISPC_REG(0x0064);
+ case OMAP_DSS_CHANNEL_DIGIT:
+ BUG();
+ case OMAP_DSS_CHANNEL_LCD2:
+ return DISPC_REG(0x0400);
+ default:
+ BUG();
+ }
+}
+
+static inline struct dispc_reg DISPC_TIMING_V(enum omap_channel channel)
+{
+ switch (channel) {
+ case OMAP_DSS_CHANNEL_LCD:
+ return DISPC_REG(0x0068);
+ case OMAP_DSS_CHANNEL_DIGIT:
+ BUG();
+ case OMAP_DSS_CHANNEL_LCD2:
+ return DISPC_REG(0x0404);
+ default:
+ BUG();
+ }
+}
+
+static inline struct dispc_reg DISPC_POL_FREQ(enum omap_channel channel)
+{
+ switch (channel) {
+ case OMAP_DSS_CHANNEL_LCD:
+ return DISPC_REG(0x006C);
+ case OMAP_DSS_CHANNEL_DIGIT:
+ BUG();
+ case OMAP_DSS_CHANNEL_LCD2:
+ return DISPC_REG(0x0408);
+ default:
+ BUG();
+ }
+}
+
+static inline struct dispc_reg DISPC_DIVISORo(enum omap_channel channel)
+{
+ switch (channel) {
+ case OMAP_DSS_CHANNEL_LCD:
+ return DISPC_REG(0x0070);
+ case OMAP_DSS_CHANNEL_DIGIT:
+ BUG();
+ case OMAP_DSS_CHANNEL_LCD2:
+ return DISPC_REG(0x040C);
+ default:
+ BUG();
+ }
+}
+
+/* Named as DISPC_SIZE_LCD, DISPC_SIZE_DIGIT and DISPC_SIZE_LCD2 in TRM */
+static inline struct dispc_reg DISPC_SIZE_MGR(enum omap_channel channel)
+{
+ switch (channel) {
+ case OMAP_DSS_CHANNEL_LCD:
+ return DISPC_REG(0x007C);
+ case OMAP_DSS_CHANNEL_DIGIT:
+ return DISPC_REG(0x0078);
+ case OMAP_DSS_CHANNEL_LCD2:
+ return DISPC_REG(0x03CC);
+ default:
+ BUG();
+ }
+}
+
+static inline struct dispc_reg DISPC_DATA_CYCLE1(enum omap_channel channel)
+{
+ switch (channel) {
+ case OMAP_DSS_CHANNEL_LCD:
+ return DISPC_REG(0x01D4);
+ case OMAP_DSS_CHANNEL_DIGIT:
+ BUG();
+ case OMAP_DSS_CHANNEL_LCD2:
+ return DISPC_REG(0x03C0);
+ default:
+ BUG();
+ }
+}
+
+static inline struct dispc_reg DISPC_DATA_CYCLE2(enum omap_channel channel)
+{
+ switch (channel) {
+ case OMAP_DSS_CHANNEL_LCD:
+ return DISPC_REG(0x01D8);
+ case OMAP_DSS_CHANNEL_DIGIT:
+ BUG();
+ case OMAP_DSS_CHANNEL_LCD2:
+ return DISPC_REG(0x03C4);
+ default:
+ BUG();
+ }
+}
+
+static inline struct dispc_reg DISPC_DATA_CYCLE3(enum omap_channel channel)
+{
+ switch (channel) {
+ case OMAP_DSS_CHANNEL_LCD:
+ return DISPC_REG(0x01DC);
+ case OMAP_DSS_CHANNEL_DIGIT:
+ BUG();
+ case OMAP_DSS_CHANNEL_LCD2:
+ return DISPC_REG(0x03C8);
+ default:
+ BUG();
+ }
+}
+
+static inline struct dispc_reg DISPC_CPR_COEF_R(enum omap_channel channel)
+{
+ switch (channel) {
+ case OMAP_DSS_CHANNEL_LCD:
+ return DISPC_REG(0x0220);
+ case OMAP_DSS_CHANNEL_DIGIT:
+ BUG();
+ case OMAP_DSS_CHANNEL_LCD2:
+ return DISPC_REG(0x03BC);
+ default:
+ BUG();
+ }
+}
+
+static inline struct dispc_reg DISPC_CPR_COEF_G(enum omap_channel channel)
+{
+ switch (channel) {
+ case OMAP_DSS_CHANNEL_LCD:
+ return DISPC_REG(0x0224);
+ case OMAP_DSS_CHANNEL_DIGIT:
+ BUG();
+ case OMAP_DSS_CHANNEL_LCD2:
+ return DISPC_REG(0x03B8);
+ default:
+ BUG();
+ }
+}
+
+static inline struct dispc_reg DISPC_CPR_COEF_B(enum omap_channel channel)
+{
+ switch (channel) {
+ case OMAP_DSS_CHANNEL_LCD:
+ return DISPC_REG(0x0228);
+ case OMAP_DSS_CHANNEL_DIGIT:
+ BUG();
+ case OMAP_DSS_CHANNEL_LCD2:
+ return DISPC_REG(0x03B4);
+ default:
+ BUG();
+ }
+}
+
/* DISPC overlay register base addresses */
static inline u16 DISPC_OVL_BASE(enum omap_plane plane)
{

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