aboutsummaryrefslogtreecommitdiffstats
path: root/drivers/net/can/pch_can.c
blob: 672718261c6872d7fb62578788bd90d54a359789 (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804
805
806
807
808
809
810
811
812
813
814
815
816
817
818
819
820
821
822
823
824
825
826
827
828
829
830
831
832
833
834
835
836
837
838
839
840
841
842
843
844
845
846
847
848
849
850
851
852
853
854
855
856
857
858
859
860
861
862
863
864
865
866
867
868
869
870
871
872
873
874
875
876
877
878
879
880
881
882
883
884
885
886
887
888
889
890
891
892
893
894
895
896
897
898
899
900
901
902
903
904
905
906
907
908
909
910
911
912
913
914
915
916
917
918
919
920
921
922
923
924
925
926
927
928
929
930
931
932
933
934
935
936
937
938
939
940
941
942
943
944
945
946
947
948
949
950
951
952
953
954
955
956
957
958
959
960
961
962
963
964
965
966
967
968
969
970
971
972
973
974
975
976
977
978
979
980
981
982
983
984
985
986
987
988
989
990
991
992
993
994
995
996
997
998
999
1000
1001
1002
1003
1004
1005
1006
1007
1008
1009
1010
1011
1012
1013
1014
1015
1016
1017
1018
1019
1020
1021
1022
1023
1024
1025
1026
1027
1028
1029
1030
1031
1032
1033
1034
1035
1036
1037
1038
1039
1040
1041
1042
1043
1044
1045
1046
1047
1048
1049
1050
1051
1052
1053
1054
1055
1056
1057
1058
1059
1060
1061
1062
1063
1064
1065
1066
1067
1068
1069
1070
1071
1072
1073
1074
1075
1076
1077
1078
1079
1080
1081
1082
1083
1084
1085
1086
1087
1088
1089
1090
1091
1092
1093
1094
1095
1096
1097
1098
1099
1100
1101
1102
1103
1104
1105
1106
1107
1108
1109
1110
1111
1112
1113
1114
1115
1116
1117
1118
1119
1120
1121
1122
1123
1124
1125
1126
1127
1128
1129
1130
1131
1132
1133
1134
1135
1136
1137
1138
1139
1140
1141
1142
1143
1144
1145
1146
1147
1148
1149
1150
1151
1152
1153
1154
1155
1156
1157
1158
1159
1160
1161
1162
1163
1164
1165
1166
1167
1168
1169
1170
1171
1172
1173
1174
1175
1176
1177
1178
1179
1180
1181
1182
1183
1184
1185
1186
1187
1188
1189
1190
1191
1192
1193
1194
1195
1196
1197
1198
1199
1200
1201
1202
1203
1204
1205
1206
1207
1208
1209
1210
1211
1212
1213
1214
1215
1216
1217
1218
1219
1220
1221
1222
1223
1224
1225
1226
1227
1228
1229
1230
1231
1232
1233
1234
1235
1236
1237
1238
1239
1240
1241
1242
1243
1244
1245
1246
1247
1248
1249
1250
1251
1252
1253
1254
1255
1256
1257
1258
1259
1260
1261
1262
1263
1264
1265
1266
1267
1268
1269
1270
1271
1272
1273
1274
1275
1276
1277
1278
1279
1280
1281
1282
1283
1284
1285
1286
1287
1288
1289
1290
1291
1292
1293
1294
1295
1296
1297
1298
1299
1300
1301
1302
1303
1304
1305
1306
1307
1308
1309
1310
1311
1312
1313
1314
1315
1316
1317
1318
1319
1320
1321
1322
1323
1324
1325
1326
1327
1328
1329
1330
1331
1332
1333
1334
1335
1336
1337
1338
1339
1340
1341
1342
1343
1344
1345
1346
1347
1348
1349
1350
1351
1352
1353
1354
1355
1356
1357
1358
1359
1360
1361
1362
1363
1364
1365
1366
1367
1368
1369
1370
1371
1372
1373
1374
1375
1376
1377
1378
1379
1380
1381
1382
1383
1384
1385
1386
1387
1388
1389
1390
1391
1392
1393
1394
1395
1396
1397
1398
1399
1400
1401
1402
1403
1404
1405
1406
1407
1408
1409
1410
1411
1412
1413
1414
1415
1416
1417
1418
1419
1420
1421
1422
1423
1424
1425
1426
1427
1428
1429
1430
1431
1432
1433
1434
1435
1436
1437
1438
1439
1440
1441
1442
1443
1444
1445
1446
1447
1448
1449
1450
1451
1452
1453
1454
1455
1456
1457
1458
1459
1460
1461
1462
1463
/*
 * Copyright (C) 1999 - 2010 Intel Corporation.
 * Copyright (C) 2010 OKI SEMICONDUCTOR Co., LTD.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; version 2 of the License.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307, USA.
 */

#include <linux/interrupt.h>
#include <linux/delay.h>
#include <linux/io.h>
#include <linux/module.h>
#include <linux/sched.h>
#include <linux/pci.h>
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/types.h>
#include <linux/errno.h>
#include <linux/netdevice.h>
#include <linux/skbuff.h>
#include <linux/can.h>
#include <linux/can/dev.h>
#include <linux/can/error.h>

#define MAX_MSG_OBJ		32
#define MSG_OBJ_RX		0 /* The receive message object flag. */
#define MSG_OBJ_TX		1 /* The transmit message object flag. */

#define ENABLE			1 /* The enable flag */
#define DISABLE			0 /* The disable flag */
#define CAN_CTRL_INIT		0x0001 /* The INIT bit of CANCONT register. */
#define CAN_CTRL_IE		0x0002 /* The IE bit of CAN control register */
#define CAN_CTRL_IE_SIE_EIE	0x000e
#define CAN_CTRL_CCE		0x0040
#define CAN_CTRL_OPT		0x0080 /* The OPT bit of CANCONT register. */
#define CAN_OPT_SILENT		0x0008 /* The Silent bit of CANOPT reg. */
#define CAN_OPT_LBACK		0x0010 /* The LoopBack bit of CANOPT reg. */
#define CAN_CMASK_RX_TX_SET	0x00f3
#define CAN_CMASK_RX_TX_GET	0x0073
#define CAN_CMASK_ALL		0xff
#define CAN_CMASK_RDWR		0x80
#define CAN_CMASK_ARB		0x20
#define CAN_CMASK_CTRL		0x10
#define CAN_CMASK_MASK		0x40
#define CAN_CMASK_NEWDAT	0x04
#define CAN_CMASK_CLRINTPND	0x08

#define CAN_IF_MCONT_NEWDAT	0x8000
#define CAN_IF_MCONT_INTPND	0x2000
#define CAN_IF_MCONT_UMASK	0x1000
#define CAN_IF_MCONT_TXIE	0x0800
#define CAN_IF_MCONT_RXIE	0x0400
#define CAN_IF_MCONT_RMTEN	0x0200
#define CAN_IF_MCONT_TXRQXT	0x0100
#define CAN_IF_MCONT_EOB	0x0080
#define CAN_IF_MCONT_DLC	0x000f
#define CAN_IF_MCONT_MSGLOST	0x4000
#define CAN_MASK2_MDIR_MXTD	0xc000
#define CAN_ID2_DIR		0x2000
#define CAN_ID_MSGVAL		0x8000

#define CAN_STATUS_INT		0x8000
#define CAN_IF_CREQ_BUSY	0x8000
#define CAN_ID2_XTD		0x4000

#define CAN_REC			0x00007f00
#define CAN_TEC			0x000000ff

#define PCH_RX_OK		0x00000010
#define PCH_TX_OK		0x00000008
#define PCH_BUS_OFF		0x00000080
#define PCH_EWARN		0x00000040
#define PCH_EPASSIV		0x00000020
#define PCH_LEC0		0x00000001
#define PCH_LEC1		0x00000002
#define PCH_LEC2		0x00000004
#define PCH_LEC_ALL		(PCH_LEC0 | PCH_LEC1 | PCH_LEC2)
#define PCH_STUF_ERR		PCH_LEC0
#define PCH_FORM_ERR		PCH_LEC1
#define PCH_ACK_ERR		(PCH_LEC0 | PCH_LEC1)
#define PCH_BIT1_ERR		PCH_LEC2
#define PCH_BIT0_ERR		(PCH_LEC0 | PCH_LEC2)
#define PCH_CRC_ERR		(PCH_LEC1 | PCH_LEC2)

/* bit position of certain controller bits. */
#define BIT_BITT_BRP		0
#define BIT_BITT_SJW		6
#define BIT_BITT_TSEG1		8
#define BIT_BITT_TSEG2		12
#define BIT_IF1_MCONT_RXIE	10
#define BIT_IF2_MCONT_TXIE	11
#define BIT_BRPE_BRPE		6
#define BIT_ES_TXERRCNT		0
#define BIT_ES_RXERRCNT		8
#define MSK_BITT_BRP		0x3f
#define MSK_BITT_SJW		0xc0
#define MSK_BITT_TSEG1		0xf00
#define MSK_BITT_TSEG2		0x7000
#define MSK_BRPE_BRPE		0x3c0
#define MSK_BRPE_GET		0x0f
#define MSK_CTRL_IE_SIE_EIE	0x07
#define MSK_MCONT_TXIE		0x08
#define MSK_MCONT_RXIE		0x10
#define PCH_CAN_NO_TX_BUFF	1
#define COUNTER_LIMIT		10

#define PCH_CAN_CLK		50000000	/* 50MHz */

/* Define the number of message object.
 * PCH CAN communications are done via Message RAM.
 * The Message RAM consists of 32 message objects. */
#define PCH_RX_OBJ_NUM		26  /* 1~ PCH_RX_OBJ_NUM is Rx*/
#define PCH_TX_OBJ_NUM		6  /* PCH_RX_OBJ_NUM is RX ~ Tx*/
#define PCH_OBJ_NUM		(PCH_TX_OBJ_NUM + PCH_RX_OBJ_NUM)

#define PCH_FIFO_THRESH		16

enum pch_can_mode {
	PCH_CAN_ENABLE,
	PCH_CAN_DISABLE,
	PCH_CAN_ALL,
	PCH_CAN_NONE,
	PCH_CAN_STOP,
	PCH_CAN_RUN
};

struct pch_can_regs {
	u32 cont;
	u32 stat;
	u32 errc;
	u32 bitt;
	u32 intr;
	u32 opt;
	u32 brpe;
	u32 reserve1;
	u32 if1_creq;
	u32 if1_cmask;
	u32 if1_mask1;
	u32 if1_mask2;
	u32 if1_id1;
	u32 if1_id2;
	u32 if1_mcont;
	u32 if1_dataa1;
	u32 if1_dataa2;
	u32 if1_datab1;
	u32 if1_datab2;
	u32 reserve2;
	u32 reserve3[12];
	u32 if2_creq;
	u32 if2_cmask;
	u32 if2_mask1;
	u32 if2_mask2;
	u32 if2_id1;
	u32 if2_id2;
	u32 if2_mcont;
	u32 if2_dataa1;
	u32 if2_dataa2;
	u32 if2_datab1;
	u32 if2_datab2;
	u32 reserve4;
	u32 reserve5[20];
	u32 treq1;
	u32 treq2;
	u32 reserve6[2];
	u32 reserve7[56];
	u32 reserve8[3];
	u32 srst;
};

struct pch_can_priv {
	struct can_priv can;
	unsigned int can_num;
	struct pci_dev *dev;
	unsigned int tx_enable[MAX_MSG_OBJ];
	unsigned int rx_enable[MAX_MSG_OBJ];
	unsigned int rx_link[MAX_MSG_OBJ];
	unsigned int int_enables;
	unsigned int int_stat;
	struct net_device *ndev;
	spinlock_t msgif_reg_lock; /* Message Interface Registers Access Lock*/
	unsigned int msg_obj[MAX_MSG_OBJ];
	struct pch_can_regs __iomem *regs;
	struct napi_struct napi;
	unsigned int tx_obj;	/* Point next Tx Obj index */
	unsigned int use_msi;
};

static struct can_bittiming_const pch_can_bittiming_const = {
	.name = KBUILD_MODNAME,
	.tseg1_min = 1,
	.tseg1_max = 16,
	.tseg2_min = 1,
	.tseg2_max = 8,
	.sjw_max = 4,
	.brp_min = 1,
	.brp_max = 1024, /* 6bit + extended 4bit */
	.brp_inc = 1,
};

static DEFINE_PCI_DEVICE_TABLE(pch_pci_tbl) = {
	{PCI_VENDOR_ID_INTEL, 0x8818, PCI_ANY_ID, PCI_ANY_ID,},
	{0,}
};
MODULE_DEVICE_TABLE(pci, pch_pci_tbl);

static inline void pch_can_bit_set(void __iomem *addr, u32 mask)
{
	iowrite32(ioread32(addr) | mask, addr);
}

static inline void pch_can_bit_clear(void __iomem *addr, u32 mask)
{
	iowrite32(ioread32(addr) & ~mask, addr);
}

static void pch_can_set_run_mode(struct pch_can_priv *priv,
				 enum pch_can_mode mode)
{
	switch (mode) {
	case PCH_CAN_RUN:
		pch_can_bit_clear(&priv->regs->cont, CAN_CTRL_INIT);
		break;

	case PCH_CAN_STOP:
		pch_can_bit_set(&priv->regs->cont, CAN_CTRL_INIT);
		break;

	default:
		dev_err(&priv->ndev->dev, "%s -> Invalid Mode.\n", __func__);
		break;
	}
}

static void pch_can_set_optmode(struct pch_can_priv *priv)
{
	u32 reg_val = ioread32(&priv->regs->opt);

	if (priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY)
		reg_val |= CAN_OPT_SILENT;

	if (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK)
		reg_val |= CAN_OPT_LBACK;

	pch_can_bit_set(&priv->regs->cont, CAN_CTRL_OPT);
	iowrite32(reg_val, &priv->regs->opt);
}

static void pch_can_set_int_custom(struct pch_can_priv *priv)
{
	/* Clearing the IE, SIE and EIE bits of Can control register. */
	pch_can_bit_clear(&priv->regs->cont, CAN_CTRL_IE_SIE_EIE);

	/* Appropriately setting them. */
	pch_can_bit_set(&priv->regs->cont,
			((priv->int_enables & MSK_CTRL_IE_SIE_EIE) << 1));
}

/* This function retrieves interrupt enabled for the CAN device. */
static void pch_can_get_int_enables(struct pch_can_priv *priv, u32 *enables)
{
	/* Obtaining the status of IE, SIE and EIE interrupt bits. */
	*enables = ((ioread32(&priv->regs->cont) & CAN_CTRL_IE_SIE_EIE) >> 1);
}

static void pch_can_set_int_enables(struct pch_can_priv *priv,
				    enum pch_can_mode interrupt_no)
{
	switch (interrupt_no) {
	case PCH_CAN_ENABLE:
		pch_can_bit_set(&priv->regs->cont, CAN_CTRL_IE);
		break;

	case PCH_CAN_DISABLE:
		pch_can_bit_clear(&priv->regs->cont, CAN_CTRL_IE);
		break;

	case PCH_CAN_ALL:
		pch_can_bit_set(&priv->regs->cont, CAN_CTRL_IE_SIE_EIE);
		break;

	case PCH_CAN_NONE:
		pch_can_bit_clear(&priv->regs->cont, CAN_CTRL_IE_SIE_EIE);
		break;

	default:
		dev_err(&priv->ndev->dev, "Invalid interrupt number.\n");
		break;
	}
}

static void pch_can_check_if_busy(u32 __iomem *creq_addr, u32 num)
{
	u32 counter = COUNTER_LIMIT;
	u32 ifx_creq;

	iowrite32(num, creq_addr);
	while (counter) {
		ifx_creq = ioread32(creq_addr) & CAN_IF_CREQ_BUSY;
		if (!ifx_creq)
			break;
		counter--;
		udelay(1);
	}
	if (!counter)
		pr_err("%s:IF1 BUSY Flag is set forever.\n", __func__);
}

static void pch_can_set_rx_enable(struct pch_can_priv *priv, u32 buff_num,
				  u32 set)
{
	unsigned long flags;

	spin_lock_irqsave(&priv->msgif_reg_lock, flags);
	/* Reading the receive buffer data from RAM to Interface1 registers */
	iowrite32(CAN_CMASK_RX_TX_GET, &priv->regs->if1_cmask);
	pch_can_check_if_busy(&priv->regs->if1_creq, buff_num);

	/* Setting the IF1MASK1 register to access MsgVal and RxIE bits */
	iowrite32(CAN_CMASK_RDWR | CAN_CMASK_ARB | CAN_CMASK_CTRL,
		  &priv->regs->if1_cmask);

	if (set == ENABLE) {
		/* Setting the MsgVal and RxIE bits */
		pch_can_bit_set(&priv->regs->if1_mcont, CAN_IF_MCONT_RXIE);
		pch_can_bit_set(&priv->regs->if1_id2, CAN_ID_MSGVAL);

	} else if (set == DISABLE) {
		/* Resetting the MsgVal and RxIE bits */
		pch_can_bit_clear(&priv->regs->if1_mcont, CAN_IF_MCONT_RXIE);
		pch_can_bit_clear(&priv->regs->if1_id2, CAN_ID_MSGVAL);
	}

	pch_can_check_if_busy(&priv->regs->if1_creq, buff_num);
	spin_unlock_irqrestore(&priv->msgif_reg_lock, flags);
}

static void pch_can_rx_enable_all(struct pch_can_priv *priv)
{
	int i;

	/* Traversing to obtain the object configured as receivers. */
	for (i = 0; i < PCH_OBJ_NUM; i++) {
		if (priv->msg_obj[i] == MSG_OBJ_RX)
			pch_can_set_rx_enable(priv, i + 1, ENABLE);
	}
}

static void pch_can_rx_disable_all(struct pch_can_priv *priv)
{
	int i;

	/* Traversing to obtain the object configured as receivers. */
	for (i = 0; i < PCH_OBJ_NUM; i++) {
		if (priv->msg_obj[i] == MSG_OBJ_RX)
			pch_can_set_rx_enable(priv, i + 1, DISABLE);
	}
}

static void pch_can_set_tx_enable(struct pch_can_priv *priv, u32 buff_num,
				 u32 set)
{
	unsigned long flags;

	spin_lock_irqsave(&priv->msgif_reg_lock, flags);
	/* Reading the Msg buffer from Message RAM to Interface2 registers. */
	iowrite32(CAN_CMASK_RX_TX_GET, &priv->regs->if2_cmask);
	pch_can_check_if_busy(&priv->regs->if2_creq, buff_num);

	/* Setting the IF2CMASK register for accessing the
		MsgVal and TxIE bits */
	iowrite32(CAN_CMASK_RDWR | CAN_CMASK_ARB | CAN_CMASK_CTRL,
		 &priv->regs->if2_cmask);

	if (set == ENABLE) {
		/* Setting the MsgVal and TxIE bits */
		pch_can_bit_set(&priv->regs->if2_mcont, CAN_IF_MCONT_TXIE);
		pch_can_bit_set(&priv->regs->if2_id2, CAN_ID_MSGVAL);
	} else if (set == DISABLE) {
		/* Resetting the MsgVal and TxIE bits. */
		pch_can_bit_clear(&priv->regs->if2_mcont, CAN_IF_MCONT_TXIE);
		pch_can_bit_clear(&priv->regs->if2_id2, CAN_ID_MSGVAL);
	}

	pch_can_check_if_busy(&priv->regs->if2_creq, buff_num);
	spin_unlock_irqrestore(&priv->msgif_reg_lock, flags);
}

static void pch_can_tx_enable_all(struct pch_can_priv *priv)
{
	int i;

	/* Traversing to obtain the object configured as transmit object. */
	for (i = 0; i < PCH_OBJ_NUM; i++) {
		if (priv->msg_obj[i] == MSG_OBJ_TX)
			pch_can_set_tx_enable(priv, i + 1, ENABLE);
	}
}

static void pch_can_tx_disable_all(struct pch_can_priv *priv)
{
	int i;

	/* Traversing to obtain the object configured as transmit object. */
	for (i = 0; i < PCH_OBJ_NUM; i++) {
		if (priv->msg_obj[i] == MSG_OBJ_TX)
			pch_can_set_tx_enable(priv, i + 1, DISABLE);
	}
}

static void pch_can_get_rx_enable(struct pch_can_priv *priv, u32 buff_num,
				 u32 *enable)
{
	unsigned long flags;

	spin_lock_irqsave(&priv->msgif_reg_lock, flags);
	iowrite32(CAN_CMASK_RX_TX_GET, &priv->regs->if1_cmask);
	pch_can_check_if_busy(&priv->regs->if1_creq, buff_num);

	if (((ioread32(&priv->regs->if1_id2)) & CAN_ID_MSGVAL) &&
			((ioread32(&priv->regs->if1_mcont)) &
			CAN_IF_MCONT_RXIE))
		*enable = ENABLE;
	else
		*enable = DISABLE;
	spin_unlock_irqrestore(&priv->msgif_reg_lock, flags);
}

static void pch_can_get_tx_enable(struct pch_can_priv *priv, u32 buff_num,
				 u32 *enable)
{
	unsigned long flags;

	spin_lock_irqsave(&priv->msgif_reg_lock, flags);
	iowrite32(CAN_CMASK_RX_TX_GET, &priv->regs->if2_cmask);
	pch_can_check_if_busy(&priv->regs->if2_creq, buff_num);

	if (((ioread32(&priv->regs->if2_id2)) & CAN_ID_MSGVAL) &&
			((ioread32(&priv->regs->if2_mcont)) &
			CAN_IF_MCONT_TXIE)) {
		*enable = ENABLE;
	} else {
		*enable = DISABLE;
	}
	spin_unlock_irqrestore(&priv->msgif_reg_lock, flags);
}

static int pch_can_int_pending(struct pch_can_priv *priv)
{
	return ioread32(&priv->regs->intr) & 0xffff;
}

static void pch_can_set_rx_buffer_link(struct pch_can_priv *priv,
				       u32 buffer_num, u32 set)
{
	unsigned long flags;

	spin_lock_irqsave(&priv->msgif_reg_lock, flags);
	iowrite32(CAN_CMASK_RX_TX_GET, &priv->regs->if1_cmask);
	pch_can_check_if_busy(&priv->regs->if1_creq, buffer_num);
	iowrite32(CAN_CMASK_RDWR | CAN_CMASK_CTRL, &priv->regs->if1_cmask);
	if (set == ENABLE)
		pch_can_bit_clear(&priv->regs->if1_mcont, CAN_IF_MCONT_EOB);
	else
		pch_can_bit_set(&priv->regs->if1_mcont, CAN_IF_MCONT_EOB);

	pch_can_check_if_busy(&priv->regs->if1_creq, buffer_num);
	spin_unlock_irqrestore(&priv->msgif_reg_lock, flags);
}

static void pch_can_get_rx_buffer_link(struct pch_can_priv *priv,
				       u32 buffer_num, u32 *link)
{
	unsigned long flags;

	spin_lock_irqsave(&priv->msgif_reg_lock, flags);
	iowrite32(CAN_CMASK_RX_TX_GET, &priv->regs->if1_cmask);
	pch_can_check_if_busy(&priv->regs->if1_creq, buffer_num);

	if (ioread32(&priv->regs->if1_mcont) & CAN_IF_MCONT_EOB)
		*link = DISABLE;
	else
		*link = ENABLE;
	spin_unlock_irqrestore(&priv->msgif_reg_lock, flags);
}

static void pch_can_clear_buffers(struct pch_can_priv *priv)
{
	int i;

	for (i = 0; i < PCH_RX_OBJ_NUM; i++) {
		iowrite32(CAN_CMASK_RX_TX_SET, &priv->regs->if1_cmask);
		iowrite32(0xffff, &priv->regs->if1_mask1);
		iowrite32(0xffff, &priv->regs->if1_mask2);
		iowrite32(0x0, &priv->regs->if1_id1);
		iowrite32(0x0, &priv->regs->if1_id2);
		iowrite32(0x0, &priv->regs->if1_mcont);
		iowrite32(0x0, &priv->regs->if1_dataa1);
		iowrite32(0x0, &priv->regs->if1_dataa2);
		iowrite32(0x0, &priv->regs->if1_datab1);
		iowrite32(0x0, &priv->regs->if1_datab2);
		iowrite32(CAN_CMASK_RDWR | CAN_CMASK_MASK |
			  CAN_CMASK_ARB | CAN_CMASK_CTRL,
			  &priv->regs->if1_cmask);
		pch_can_check_if_busy(&priv->regs->if1_creq, i+1);
	}

	for (i = i;  i < PCH_OBJ_NUM; i++) {
		iowrite32(CAN_CMASK_RX_TX_SET, &priv->regs->if2_cmask);
		iowrite32(0xffff, &priv->regs->if2_mask1);
		iowrite32(0xffff, &priv->regs->if2_mask2);
		iowrite32(0x0, &priv->regs->if2_id1);
		iowrite32(0x0, &priv->regs->if2_id2);
		iowrite32(0x0, &priv->regs->if2_mcont);
		iowrite32(0x0, &priv->regs->if2_dataa1);
		iowrite32(0x0, &priv->regs->if2_dataa2);
		iowrite32(0x0, &priv->regs->if2_datab1);
		iowrite32(0x0, &priv->regs->if2_datab2);
		iowrite32(CAN_CMASK_RDWR | CAN_CMASK_MASK |
			  CAN_CMASK_ARB | CAN_CMASK_CTRL,
			  &priv->regs->if2_cmask);
		pch_can_check_if_busy(&priv->regs->if2_creq, i+1);
	}
}

static void pch_can_config_rx_tx_buffers(struct pch_can_priv *priv)
{
	int i;
	unsigned long flags;

	spin_lock_irqsave(&priv->msgif_reg_lock, flags);

	for (i = 0; i < PCH_OBJ_NUM; i++) {
		if (priv->msg_obj[i] == MSG_OBJ_RX) {
			iowrite32(CAN_CMASK_RX_TX_GET,
				&priv->regs->if1_cmask);
			pch_can_check_if_busy(&priv->regs->if1_creq, i+1);

			iowrite32(0x0, &priv->regs->if1_id1);
			iowrite32(0x0, &priv->regs->if1_id2);

			pch_can_bit_set(&priv->regs->if1_mcont,
					CAN_IF_MCONT_UMASK);

			/* Set FIFO mode set to 0 except last Rx Obj*/
			pch_can_bit_clear(&priv->regs->if1_mcont,
					  CAN_IF_MCONT_EOB);
			/* In case FIFO mode, Last EoB of Rx Obj must be 1 */
			if (i == (PCH_RX_OBJ_NUM - 1))
				pch_can_bit_set(&priv->regs->if1_mcont,
						  CAN_IF_MCONT_EOB);

			iowrite32(0, &priv->regs->if1_mask1);
			pch_can_bit_clear(&priv->regs->if1_mask2,
					  0x1fff | CAN_MASK2_MDIR_MXTD);

			/* Setting CMASK for writing */
			iowrite32(CAN_CMASK_RDWR | CAN_CMASK_MASK |
				  CAN_CMASK_ARB | CAN_CMASK_CTRL,
				  &priv->regs->if1_cmask);

			pch_can_check_if_busy(&priv->regs->if1_creq, i+1);
		} else if (priv->msg_obj[i] == MSG_OBJ_TX) {
			iowrite32(CAN_CMASK_RX_TX_GET,
				&priv->regs->if2_cmask);
			pch_can_check_if_busy(&priv->regs->if2_creq, i+1);

			/* Resetting DIR bit for reception */
			iowrite32(0x0, &priv->regs->if2_id1);
			iowrite32(0x0, &priv->regs->if2_id2);
			pch_can_bit_set(&priv->regs->if2_id2, CAN_ID2_DIR);

			/* Setting EOB bit for transmitter */
			iowrite32(CAN_IF_MCONT_EOB, &priv->regs->if2_mcont);

			pch_can_bit_set(&priv->regs->if2_mcont,
					CAN_IF_MCONT_UMASK);

			iowrite32(0, &priv->regs->if2_mask1);
			pch_can_bit_clear(&priv->regs->if2_mask2, 0x1fff);

			/* Setting CMASK for writing */
			iowrite32(CAN_CMASK_RDWR | CAN_CMASK_MASK |
				  CAN_CMASK_ARB | CAN_CMASK_CTRL,
				  &priv->regs->if2_cmask);

			pch_can_check_if_busy(&priv->regs->if2_creq, i+1);
		}
	}
	spin_unlock_irqrestore(&priv->msgif_reg_lock, flags);
}

static void pch_can_init(struct pch_can_priv *priv)
{
	/* Stopping the Can device. */
	pch_can_set_run_mode(priv, PCH_CAN_STOP);

	/* Clearing all the message object buffers. */
	pch_can_clear_buffers(priv);

	/* Configuring the respective message object as either rx/tx object. */
	pch_can_config_rx_tx_buffers(priv);

	/* Enabling the interrupts. */
	pch_can_set_int_enables(priv, PCH_CAN_ALL);
}

static void pch_can_release(struct pch_can_priv *priv)
{
	/* Stooping the CAN device. */
	pch_can_set_run_mode(priv, PCH_CAN_STOP);

	/* Disabling the interrupts. */
	pch_can_set_int_enables(priv, PCH_CAN_NONE);

	/* Disabling all the receive object. */
	pch_can_rx_disable_all(priv);

	/* Disabling all the transmit object. */
	pch_can_tx_disable_all(priv);
}

/* This function clears interrupt(s) from the CAN device. */
static void pch_can_int_clr(struct pch_can_priv *priv, u32 mask)
{
	if (mask == CAN_STATUS_INT) {
		ioread32(&priv->regs->stat);
		return;
	}

	/* Clear interrupt for transmit object */
	if (priv->msg_obj[mask - 1] == MSG_OBJ_TX) {
		/* Setting CMASK for clearing interrupts for
					 frame transmission. */
		iowrite32(CAN_CMASK_RDWR | CAN_CMASK_CTRL | CAN_CMASK_ARB,
			  &priv->regs->if2_cmask);

		/* Resetting the ID registers. */
		pch_can_bit_set(&priv->regs->if2_id2,
			       CAN_ID2_DIR | (0x7ff << 2));
		iowrite32(0x0, &priv->regs->if2_id1);

		/* Claring NewDat, TxRqst & IntPnd */
		pch_can_bit_clear(&priv->regs->if2_mcont,
				  CAN_IF_MCONT_NEWDAT | CAN_IF_MCONT_INTPND |
				  CAN_IF_MCONT_TXRQXT);
		pch_can_check_if_busy(&priv->regs->if2_creq, mask);
	} else if (priv->msg_obj[mask - 1] == MSG_OBJ_RX) {
		/* Setting CMASK for clearing the reception interrupts. */
		iowrite32(CAN_CMASK_RDWR | CAN_CMASK_CTRL | CAN_CMASK_ARB,
			  &priv->regs->if1_cmask);

		/* Clearing the Dir bit. */
		pch_can_bit_clear(&priv->regs->if1_id2, CAN_ID2_DIR);

		/* Clearing NewDat & IntPnd */
		pch_can_bit_clear(&priv->regs->if1_mcont,
				  CAN_IF_MCONT_NEWDAT | CAN_IF_MCONT_INTPND);

		pch_can_check_if_busy(&priv->regs->if1_creq, mask);
	}
}

static int pch_can_get_buffer_status(struct pch_can_priv *priv)
{
	return (ioread32(&priv->regs->treq1) & 0xffff) |
	       ((ioread32(&priv->regs->treq2) & 0xffff) << 16);
}

static void pch_can_reset(struct pch_can_priv *priv)
{
	/* write to sw reset register */
	iowrite32(1, &priv->regs->srst);
	iowrite32(0, &priv->regs->srst);
}

static void pch_can_error(struct net_device *ndev, u32 status)
{
	struct sk_buff *skb;
	struct pch_can_priv *priv = netdev_priv(ndev);
	struct can_frame *cf;
	u32 errc;
	struct net_device_stats *stats = &(priv->ndev->stats);
	enum can_state state = priv->can.state;

	skb = alloc_can_err_skb(ndev, &cf);
	if (!skb)
		return;

	if (status & PCH_BUS_OFF) {
		pch_can_tx_disable_all(priv);
		pch_can_rx_disable_all(priv);
		state = CAN_STATE_BUS_OFF;
		cf->can_id |= CAN_ERR_BUSOFF;
		can_bus_off(ndev);
		pch_can_set_run_mode(priv, PCH_CAN_RUN);
		dev_err(&ndev->dev, "%s -> Bus Off occurres.\n", __func__);
	}

	/* Warning interrupt. */
	if (status & PCH_EWARN) {
		state = CAN_STATE_ERROR_WARNING;
		priv->can.can_stats.error_warning++;
		cf->can_id |= CAN_ERR_CRTL;
		errc = ioread32(&priv->regs->errc);
		if (((errc & CAN_REC) >> 8) > 96)
			cf->data[1] |= CAN_ERR_CRTL_RX_WARNING;
		if ((errc & CAN_TEC) > 96)
			cf->data[1] |= CAN_ERR_CRTL_TX_WARNING;
		dev_warn(&ndev->dev,
			"%s -> Error Counter is more than 96.\n", __func__);
	}
	/* Error passive interrupt. */
	if (status & PCH_EPASSIV) {
		priv->can.can_stats.error_passive++;
		state = CAN_STATE_ERROR_PASSIVE;
		cf->can_id |= CAN_ERR_CRTL;
		errc = ioread32(&priv->regs->errc);
		if (((errc & CAN_REC) >> 8) > 127)
			cf->data[1] |= CAN_ERR_CRTL_RX_PASSIVE;
		if ((errc & CAN_TEC) > 127)
			cf->data[1] |= CAN_ERR_CRTL_TX_PASSIVE;
		dev_err(&ndev->dev,
			"%s -> CAN controller is ERROR PASSIVE .\n", __func__);
	}

	if (status & PCH_LEC_ALL) {
		priv->can.can_stats.bus_error++;
		stats->rx_errors++;
		switch (status & PCH_LEC_ALL) {
		case PCH_STUF_ERR:
			cf->data[2] |= CAN_ERR_PROT_STUFF;
			break;
		case PCH_FORM_ERR:
			cf->data[2] |= CAN_ERR_PROT_FORM;
			break;
		case PCH_ACK_ERR:
			cf->data[2] |= CAN_ERR_PROT_LOC_ACK |
				       CAN_ERR_PROT_LOC_ACK_DEL;
			break;
		case PCH_BIT1_ERR:
		case PCH_BIT0_ERR:
			cf->data[2] |= CAN_ERR_PROT_BIT;
			break;
		case PCH_CRC_ERR:
			cf->data[2] |= CAN_ERR_PROT_LOC_CRC_SEQ |
				       CAN_ERR_PROT_LOC_CRC_DEL;
			break;
		default:
			iowrite32(status | PCH_LEC_ALL, &priv->regs->stat);
			break;
		}

	}

	priv->can.state = state;
	netif_rx(skb);

	stats->rx_packets++;
	stats->rx_bytes += cf->can_dlc;
}

static irqreturn_t pch_can_interrupt(int irq, void *dev_id)
{
	struct net_device *ndev = (struct net_device *)dev_id;
	struct pch_can_priv *priv = netdev_priv(ndev);

	pch_can_set_int_enables(priv, PCH_CAN_NONE);

	napi_schedule(&priv->napi);

	return IRQ_HANDLED;
}

static int pch_can_rx_normal(struct net_device *ndev, u32 int_stat)
{
	u32 reg;
	canid_t id;
	u32 ide;
	u32 rtr;
	int i, j, k;
	int rcv_pkts = 0;
	struct sk_buff *skb;
	struct can_frame *cf;
	struct pch_can_priv *priv = netdev_priv(ndev);
	struct net_device_stats *stats = &(priv->ndev->stats);

	/* Reading the messsage object from the Message RAM */
	iowrite32(CAN_CMASK_RX_TX_GET, &priv->regs->if1_cmask);
	pch_can_check_if_busy(&priv->regs->if1_creq, int_stat);

	/* Reading the MCONT register. */
	reg = ioread32(&priv->regs->if1_mcont);
	reg &= 0xffff;

	for (k = int_stat; !(reg & CAN_IF_MCONT_EOB); k++) {
		/* If MsgLost bit set. */
		if (reg & CAN_IF_MCONT_MSGLOST) {
			dev_err(&priv->ndev->dev, "Msg Obj is overwritten.\n");
			pch_can_bit_clear(&priv->regs->if1_mcont,
					  CAN_IF_MCONT_MSGLOST);
			iowrite32(CAN_CMASK_RDWR | CAN_CMASK_CTRL,
				  &priv->regs->if1_cmask);
			pch_can_check_if_busy(&priv->regs->if1_creq, k);

			skb = alloc_can_err_skb(ndev, &cf);
			if (!skb)
				return -ENOMEM;

			priv->can.can_stats.error_passive++;
			priv->can.state = CAN_STATE_ERROR_PASSIVE;
			cf->can_id |= CAN_ERR_CRTL;
			cf->data[1] |= CAN_ERR_CRTL_RX_OVERFLOW;
			cf->data[2] |= CAN_ERR_PROT_OVERLOAD;
			stats->rx_packets++;
			stats->rx_bytes += cf->can_dlc;

			netif_receive_skb(skb);
			rcv_pkts++;
			goto RX_NEXT;
		}
		if (!(reg & CAN_IF_MCONT_NEWDAT))
			goto RX_NEXT;

		skb = alloc_can_skb(priv->ndev, &cf);
		if (!skb)
			return -ENOMEM;

		/* Get Received data */
		ide = ((ioread32(&priv->regs->if1_id2)) & CAN_ID2_XTD) >> 14;
		if (ide) {
			id = (ioread32(&priv->regs->if1_id1) & 0xffff);
			id |= (((ioread32(&priv->regs->if1_id2)) &
					    0x1fff) << 16);
			cf->can_id = (id & CAN_EFF_MASK) | CAN_EFF_FLAG;
		} else {
			id = (((ioread32(&priv->regs->if1_id2)) &
					  (CAN_SFF_MASK << 2)) >> 2);
			cf->can_id = (id & CAN_SFF_MASK);
		}

		rtr = (ioread32(&priv->regs->if1_id2) &  CAN_ID2_DIR);
		if (rtr) {
			cf->can_dlc = 0;
			cf->can_id |= CAN_RTR_FLAG;
		} else {
			cf->can_dlc = ((ioread32(&priv->regs->if1_mcont)) &
						   0x0f);
		}

		for (i = 0, j = 0; i < cf->can_dlc; j++) {
			reg = ioread32(&priv->regs->if1_dataa1 + j*4);
			cf->data[i++] = cpu_to_le32(reg & 0xff);
			if (i == cf->can_dlc)
				break;
			cf->data[i++] = cpu_to_le32((reg >> 8) & 0xff);
		}

		netif_receive_skb(skb);
		rcv_pkts++;
		stats->rx_packets++;
		stats->rx_bytes += cf->can_dlc;

		if (k < PCH_FIFO_THRESH) {
			iowrite32(CAN_CMASK_RDWR | CAN_CMASK_CTRL |
				  CAN_CMASK_ARB, &priv->regs->if1_cmask);

			/* Clearing the Dir bit. */
			pch_can_bit_clear(&priv->regs->if1_id2, CAN_ID2_DIR);

			/* Clearing NewDat & IntPnd */
			pch_can_bit_clear(&priv->regs->if1_mcont,
					  CAN_IF_MCONT_INTPND);
			pch_can_check_if_busy(&priv->regs->if1_creq, k);
		} else if (k > PCH_FIFO_THRESH) {
			pch_can_int_clr(priv, k);
		} else if (k == PCH_FIFO_THRESH) {
			int cnt;
			for (cnt = 0; cnt < PCH_FIFO_THRESH; cnt++)
				pch_can_int_clr(priv, cnt+1);
		}
RX_NEXT:
		/* Reading the messsage object from the Message RAM */
		iowrite32(CAN_CMASK_RX_TX_GET, &priv->regs->if1_cmask);
		pch_can_check_if_busy(&priv->regs->if1_creq, k + 1);
		reg = ioread32(&priv->regs->if1_mcont);
	}

	return rcv_pkts;
}
static int pch_can_rx_poll(struct napi_struct *napi, int quota)
{
	struct net_device *ndev = napi->dev;
	struct pch_can_priv *priv = netdev_priv(ndev);
	struct net_device_stats *stats = &(priv->ndev->stats);
	u32 dlc;
	u32 int_stat;
	int rcv_pkts = 0;
	u32 reg_stat;
	unsigned long flags;

	int_stat = pch_can_int_pending(priv);
	if (!int_stat)
		return 0;

INT_STAT:
	if (int_stat == CAN_STATUS_INT) {
		reg_stat = ioread32(&priv->regs->stat);
		if (reg_stat & (PCH_BUS_OFF | PCH_LEC_ALL)) {
			if ((reg_stat & PCH_LEC_ALL) != PCH_LEC_ALL)
				pch_can_error(ndev, reg_stat);
		}

		if (reg_stat & PCH_TX_OK) {
			spin_lock_irqsave(&priv->msgif_reg_lock, flags);
			iowrite32(CAN_CMASK_RX_TX_GET, &priv->regs->if2_cmask);
			pch_can_check_if_busy(&priv->regs->if2_creq,
					       ioread32(&priv->regs->intr));
			spin_unlock_irqrestore(&priv->msgif_reg_lock, flags);
			pch_can_bit_clear(&priv->regs->stat, PCH_TX_OK);
		}

		if (reg_stat & PCH_RX_OK)
			pch_can_bit_clear(&priv->regs->stat, PCH_RX_OK);

		int_stat = pch_can_int_pending(priv);
		if (int_stat == CAN_STATUS_INT)
			goto INT_STAT;
	}

MSG_OBJ:
	if ((int_stat >= 1) && (int_stat <= PCH_RX_OBJ_NUM)) {
		spin_lock_irqsave(&priv->msgif_reg_lock, flags);
		rcv_pkts = pch_can_rx_normal(ndev, int_stat);
		spin_unlock_irqrestore(&priv->msgif_reg_lock, flags);
		if (rcv_pkts < 0)
			return 0;
	} else if ((int_stat > PCH_RX_OBJ_NUM) && (int_stat <= PCH_OBJ_NUM)) {
		if (priv->msg_obj[int_stat - 1] == MSG_OBJ_TX) {
			/* Handle transmission interrupt */
			can_get_echo_skb(ndev, int_stat - PCH_RX_OBJ_NUM - 1);
			spin_lock_irqsave(&priv->msgif_reg_lock, flags);
			iowrite32(CAN_CMASK_RX_TX_GET | CAN_CMASK_CLRINTPND,
				  &priv->regs->if2_cmask);
			dlc = ioread32(&priv->regs->if2_mcont) &
				       CAN_IF_MCONT_DLC;
			pch_can_check_if_busy(&priv->regs->if2_creq, int_stat);
			spin_unlock_irqrestore(&priv->msgif_reg_lock, flags);
			if (dlc > 8)
				dlc = 8;
			stats->tx_bytes += dlc;
			stats->tx_packets++;
		}
	}

	int_stat = pch_can_int_pending(priv);
	if (int_stat == CAN_STATUS_INT)
		goto INT_STAT;
	else if (int_stat >= 1 && int_stat <= 32)
		goto MSG_OBJ;

	napi_complete(napi);
	pch_can_set_int_enables(priv, PCH_CAN_ALL);

	return rcv_pkts;
}

static int pch_set_bittiming(struct net_device *ndev)
{
	struct pch_can_priv *priv = netdev_priv(ndev);
	const struct can_bittiming *bt = &priv->can.bittiming;
	u32 canbit;
	u32 bepe;
	u32 brp;

	/* Setting the CCE bit for accessing the Can Timing register. */
	pch_can_bit_set(&priv->regs->cont, CAN_CTRL_CCE);

	brp = (bt->tq) / (1000000000/PCH_CAN_CLK) - 1;
	canbit = brp & MSK_BITT_BRP;
	canbit |= (bt->sjw - 1) << BIT_BITT_SJW;
	canbit |= (bt->phase_seg1 + bt->prop_seg - 1) << BIT_BITT_TSEG1;
	canbit |= (bt->phase_seg2 - 1) << BIT_BITT_TSEG2;
	bepe = (brp & MSK_BRPE_BRPE) >> BIT_BRPE_BRPE;
	iowrite32(canbit, &priv->regs->bitt);
	iowrite32(bepe, &priv->regs->brpe);
	pch_can_bit_clear(&priv->regs->cont, CAN_CTRL_CCE);

	return 0;
}

static void pch_can_start(struct net_device *ndev)
{
	struct pch_can_priv *priv = netdev_priv(ndev);

	if (priv->can.state != CAN_STATE_STOPPED)
		pch_can_reset(priv);

	pch_set_bittiming(ndev);
	pch_can_set_optmode(priv);

	pch_can_tx_enable_all(priv);
	pch_can_rx_enable_all(priv);

	/* Setting the CAN to run mode. */
	pch_can_set_run_mode(priv, PCH_CAN_RUN);

	priv->can.state = CAN_STATE_ERROR_ACTIVE;

	return;
}

static int pch_can_do_set_mode(struct net_device *ndev, enum can_mode mode)
{
	int ret = 0;

	switch (mode) {
	case CAN_MODE_START:
		pch_can_start(ndev);
		netif_wake_queue(ndev);
		break;
	default:
		ret = -EOPNOTSUPP;
		break;
	}

	return ret;
}

static int pch_can_open(struct net_device *ndev)
{
	struct pch_can_priv *priv = netdev_priv(ndev);
	int retval;

	retval = pci_enable_msi(priv->dev);
	if (retval) {
		dev_info(&ndev->dev, "PCH CAN opened without MSI\n");
		priv->use_msi = 0;
	} else {
		dev_info(&ndev->dev, "PCH CAN opened with MSI\n");
		priv->use_msi = 1;
	}

	/* Regsitering the interrupt. */
	retval = request_irq(priv->dev->irq, pch_can_interrupt, IRQF_SHARED,
			     ndev->name, ndev);
	if (retval) {
		dev_err(&ndev->dev, "request_irq failed.\n");
		goto req_irq_err;
	}

	/* Open common can device */
	retval = open_candev(ndev);
	if (retval) {
		dev_err(ndev->dev.parent, "open_candev() failed %d\n", retval);
		goto err_open_candev;
	}

	pch_can_init(priv);
	pch_can_start(ndev);
	napi_enable(&priv->napi);
	netif_start_queue(ndev);

	return 0;

err_open_candev:
	free_irq(priv->dev->irq, ndev);
req_irq_err:
	if (priv->use_msi)
		pci_disable_msi(priv->dev);

	pch_can_release(priv);

	return retval;
}

static int pch_close(struct net_device *ndev)
{
	struct pch_can_priv *priv = netdev_priv(ndev);

	netif_stop_queue(ndev);
	napi_disable(&priv->napi);
	pch_can_release(priv);
	free_irq(priv->dev->irq, ndev);
	if (priv->use_msi)
		pci_disable_msi(priv->dev);
	close_candev(ndev);
	priv->can.state = CAN_STATE_STOPPED;
	return 0;
}

static int pch_get_msg_obj_sts(struct net_device *ndev, u32 obj_id)
{
	u32 buffer_status = 0;
	struct pch_can_priv *priv = netdev_priv(ndev);

	/* Getting the message object status. */
	buffer_status = (u32) pch_can_get_buffer_status(priv);

	return buffer_status & obj_id;
}


static netdev_tx_t pch_xmit(struct sk_buff *skb, struct net_device *ndev)
{
	int i, j;
	unsigned long flags;
	struct pch_can_priv *priv = netdev_priv(ndev);
	struct can_frame *cf = (struct can_frame *)skb->data;
	int tx_buffer_avail = 0;

	if (can_dropped_invalid_skb(ndev, skb))
		return NETDEV_TX_OK;

	if (priv->tx_obj == (PCH_OBJ_NUM + 1)) { /* Point tail Obj */
		while (pch_get_msg_obj_sts(ndev, (((1 << PCH_TX_OBJ_NUM)-1) <<
					   PCH_RX_OBJ_NUM)))
			udelay(500);

		priv->tx_obj = PCH_RX_OBJ_NUM + 1; /* Point head of Tx Obj ID */
		tx_buffer_avail = priv->tx_obj; /* Point Tail of Tx Obj */
	} else {
		tx_buffer_avail = priv->tx_obj;
	}
	priv->tx_obj++;

	/* Attaining the lock. */
	spin_lock_irqsave(&priv->msgif_reg_lock, flags);

	/* Reading the Msg Obj from the Msg RAM to the Interface register. */
	iowrite32(CAN_CMASK_RX_TX_GET, &priv->regs->if2_cmask);
	pch_can_check_if_busy(&priv->regs->if2_creq, tx_buffer_avail);

	/* Setting the CMASK register. */
	pch_can_bit_set(&priv->regs->if2_cmask, CAN_CMASK_ALL);

	/* If ID extended is set. */
	pch_can_bit_clear(&priv->regs->if2_id1, 0xffff);
	pch_can_bit_clear(&priv->regs->if2_id2, 0x1fff | CAN_ID2_XTD);
	if (cf->can_id & CAN_EFF_FLAG) {
		pch_can_bit_set(&priv->regs->if2_id1, cf->can_id & 0xffff);
		pch_can_bit_set(&priv->regs->if2_id2,
				((cf->can_id >> 16) & 0x1fff) | CAN_ID2_XTD);
	} else {
		pch_can_bit_set(&priv->regs->if2_id1, 0);
		pch_can_bit_set(&priv->regs->if2_id2,
				(cf->can_id & CAN_SFF_MASK) << 2);
	}

	/* If remote frame has to be transmitted.. */
	if (cf->can_id & CAN_RTR_FLAG)
		pch_can_bit_clear(&priv->regs->if2_id2, CAN_ID2_DIR);

	for (i = 0, j = 0; i < cf->can_dlc; j++) {
		iowrite32(le32_to_cpu(cf->data[i++]),
			 (&priv->regs->if2_dataa1) + j*4);
		if (i == cf->can_dlc)
			break;
		iowrite32(le32_to_cpu(cf->data[i++] << 8),
			 (&priv->regs->if2_dataa1) + j*4);
	}

	can_put_echo_skb(skb, ndev, tx_buffer_avail - PCH_RX_OBJ_NUM - 1);

	/* Updating the size of the data. */
	pch_can_bit_clear(&priv->regs->if2_mcont, 0x0f);
	pch_can_bit_set(&priv->regs->if2_mcont, cf->can_dlc);

	/* Clearing IntPend, NewDat & TxRqst */
	pch_can_bit_clear(&priv->regs->if2_mcont,
			  CAN_IF_MCONT_NEWDAT | CAN_IF_MCONT_INTPND |
			  CAN_IF_MCONT_TXRQXT);

	/* Setting NewDat, TxRqst bits */
	pch_can_bit_set(&priv->regs->if2_mcont,
			CAN_IF_MCONT_NEWDAT | CAN_IF_MCONT_TXRQXT);

	pch_can_check_if_busy(&priv->regs->if2_creq, tx_buffer_avail);

	spin_unlock_irqrestore(&priv->msgif_reg_lock, flags);

	return NETDEV_TX_OK;
}

static const struct net_device_ops pch_can_netdev_ops = {
	.ndo_open		= pch_can_open,
	.ndo_stop		= pch_close,
	.ndo_start_xmit		= pch_xmit,
};

static void __devexit pch_can_remove(struct pci_dev *pdev)
{
	struct net_device *ndev = pci_get_drvdata(pdev);
	struct pch_can_priv *priv = netdev_priv(ndev);

	unregister_candev(priv->ndev);
	free_candev(priv->ndev);
	pci_iounmap(pdev, priv->regs);
	pci_release_regions(pdev);
	pci_disable_device(pdev);
	pci_set_drvdata(pdev, NULL);
	pch_can_reset(priv);
}

#ifdef CONFIG_PM
static int pch_can_suspend(struct pci_dev *pdev, pm_message_t state)
{
	int i;			/* Counter variable. */
	int retval;		/* Return value. */
	u32 buf_stat;	/* Variable for reading the transmit buffer status. */
	u32 counter = 0xFFFFFF;

	struct net_device *dev = pci_get_drvdata(pdev);
	struct pch_can_priv *priv = netdev_priv(dev);

	/* Stop the CAN controller */
	pch_can_set_run_mode(priv, PCH_CAN_STOP);

	/* Indicate that we are aboutto/in suspend */
	priv->can.state = CAN_STATE_SLEEPING;

	/* Waiting for all transmission to complete. */
	while (counter) {
		buf_stat = pch_can_get_buffer_status(priv);
		if (!buf_stat)
			break;
		counter--;
		udelay(1);
	}
	if (!counter)
		dev_err(&pdev->dev, "%s -> Transmission time out.\n", __func__);

	/* Save interrupt configuration and then disable them */
	pch_can_get_int_enables(priv, &(priv->int_enables));
	pch_can_set_int_enables(priv, PCH_CAN_DISABLE);

	/* Save Tx buffer enable state */
	for (i = 0; i < PCH_OBJ_NUM; i++) {
		if (priv->msg_obj[i] == MSG_OBJ_TX)
			pch_can_get_tx_enable(priv, i + 1,
					      &(priv->tx_enable[i]));
	}

	/* Disable all Transmit buffers */
	pch_can_tx_disable_all(priv);

	/* Save Rx buffer enable state */
	for (i = 0; i < PCH_OBJ_NUM; i++) {
		if (priv->msg_obj[i] == MSG_OBJ_RX) {
			pch_can_get_rx_enable(priv, i + 1,
						&(priv->rx_enable[i]));
			pch_can_get_rx_buffer_link(priv, i + 1,
						&(priv->rx_link[i]));
		}
	}

	/* Disable all Receive buffers */
	pch_can_rx_disable_all(priv);
	retval = pci_save_state(pdev);
	if (retval) {
		dev_err(&pdev->dev, "pci_save_state failed.\n");
	} else {
		pci_enable_wake(pdev, PCI_D3hot, 0);
		pci_disable_device(pdev);
		pci_set_power_state(pdev, pci_choose_state(pdev, state));
	}

	return retval;
}

static int pch_can_resume(struct pci_dev *pdev)
{
	int i;			/* Counter variable. */
	int retval;		/* Return variable. */
	struct net_device *dev = pci_get_drvdata(pdev);
	struct pch_can_priv *priv = netdev_priv(dev);

	pci_set_power_state(pdev, PCI_D0);
	pci_restore_state(pdev);
	retval = pci_enable_device(pdev);
	if (retval) {
		dev_err(&pdev->dev, "pci_enable_device failed.\n");
		return retval;
	}

	pci_enable_wake(pdev, PCI_D3hot, 0);

	priv->can.state = CAN_STATE_ERROR_ACTIVE;

	/* Disabling all interrupts. */
	pch_can_set_int_enables(priv, PCH_CAN_DISABLE);

	/* Setting the CAN device in Stop Mode. */
	pch_can_set_run_mode(priv, PCH_CAN_STOP);

	/* Configuring the transmit and receive buffers. */
	pch_can_config_rx_tx_buffers(priv);

	/* Restore the CAN state */
	pch_set_bittiming(dev);

	/* Listen/Active */
	pch_can_set_optmode(priv);

	/* Enabling the transmit buffer. */
	for (i = 0; i < PCH_OBJ_NUM; i++) {
		if (priv->msg_obj[i] == MSG_OBJ_TX) {
			pch_can_set_tx_enable(priv, i + 1,
					      priv->tx_enable[i]);
		}
	}

	/* Configuring the receive buffer and enabling them. */
	for (i = 0; i < PCH_OBJ_NUM; i++) {
		if (priv->msg_obj[i] == MSG_OBJ_RX) {
			/* Restore buffer link */
			pch_can_set_rx_buffer_link(priv, i + 1,
						   priv->rx_link[i]);

			/* Restore buffer enables */
			pch_can_set_rx_enable(priv, i + 1, priv->rx_enable[i]);
		}
	}

	/* Enable CAN Interrupts */
	pch_can_set_int_custom(priv);

	/* Restore Run Mode */
	pch_can_set_run_mode(priv, PCH_CAN_RUN);

	return retval;
}
#else
#define pch_can_suspend NULL
#define pch_can_resume NULL
#endif

static int pch_can_get_berr_counter(const struct net_device *dev,
				    struct can_berr_counter *bec)
{
	struct pch_can_priv *priv = netdev_priv(dev);

	bec->txerr = ioread32(&priv->regs->errc) & CAN_TEC;
	bec->rxerr = (ioread32(&priv->regs->errc) & CAN_REC) >> 8;

	return 0;
}

static int __devinit pch_can_probe(struct pci_dev *pdev,
				   const struct pci_device_id *id)
{
	struct net_device *ndev;
	struct pch_can_priv *priv;
	int rc;
	int index;
	void __iomem *addr;

	rc = pci_enable_device(pdev);
	if (rc) {
		dev_err(&pdev->dev, "Failed pci_enable_device %d\n", rc);
		goto probe_exit_endev;
	}

	rc = pci_request_regions(pdev, KBUILD_MODNAME);
	if (rc) {
		dev_err(&pdev->dev, "Failed pci_request_regions %d\n", rc);
		goto probe_exit_pcireq;
	}

	addr = pci_iomap(pdev, 1, 0);
	if (!addr) {
		rc = -EIO;
		dev_err(&pdev->dev, "Failed pci_iomap\n");
		goto probe_exit_ipmap;
	}

	ndev = alloc_candev(sizeof(struct pch_can_priv), PCH_TX_OBJ_NUM);
	if (!ndev) {
		rc = -ENOMEM;
		dev_err(&pdev->dev, "Failed alloc_candev\n");
		goto probe_exit_alloc_candev;
	}

	priv = netdev_priv(ndev);
	priv->ndev = ndev;
	priv->regs = addr;
	priv->dev = pdev;
	priv->can.bittiming_const = &pch_can_bittiming_const;
	priv->can.do_set_mode = pch_can_do_set_mode;
	priv->can.do_get_berr_counter = pch_can_get_berr_counter;
	priv->can.ctrlmode_supported = CAN_CTRLMODE_LISTENONLY |
				       CAN_CTRLMODE_LOOPBACK;
	priv->tx_obj = PCH_RX_OBJ_NUM + 1; /* Point head of Tx Obj */

	ndev->irq = pdev->irq;
	ndev->flags |= IFF_ECHO;

	pci_set_drvdata(pdev, ndev);
	SET_NETDEV_DEV(ndev, &pdev->dev);
	ndev->netdev_ops = &pch_can_netdev_ops;

	priv->can.clock.freq = PCH_CAN_CLK; /* Hz */
	for (index = 0; index < PCH_RX_OBJ_NUM;)
		priv->msg_obj[index++] = MSG_OBJ_RX;

	for (index = index;  index < PCH_OBJ_NUM;)
		priv->msg_obj[index++] = MSG_OBJ_TX;

	netif_napi_add(ndev, &priv->napi, pch_can_rx_poll, PCH_RX_OBJ_NUM);

	rc = register_candev(ndev);
	if (rc) {
		dev_err(&pdev->dev, "Failed register_candev %d\n", rc);
		goto probe_exit_reg_candev;
	}

	return 0;

probe_exit_reg_candev:
	free_candev(ndev);
probe_exit_alloc_candev:
	pci_iounmap(pdev, addr);
probe_exit_ipmap:
	pci_release_regions(pdev);
probe_exit_pcireq:
	pci_disable_device(pdev);
probe_exit_endev:
	return rc;
}

static struct pci_driver pch_can_pci_driver = {
	.name = "pch_can",
	.id_table = pch_pci_tbl,
	.probe = pch_can_probe,
	.remove = __devexit_p(pch_can_remove),
	.suspend = pch_can_suspend,
	.resume = pch_can_resume,
};

static int __init pch_can_pci_init(void)
{
	return pci_register_driver(&pch_can_pci_driver);
}
module_init(pch_can_pci_init);

static void __exit pch_can_pci_exit(void)
{
	pci_unregister_driver(&pch_can_pci_driver);
}
module_exit(pch_can_pci_exit);

MODULE_DESCRIPTION("Controller Area Network Driver");
MODULE_LICENSE("GPL v2");
MODULE_VERSION("0.94");

Privacy Policy