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authorAnurag Kumar Vulisha <anurag.kumar.vulisha@xilinx.com>2018-12-18 19:15:32 +0530
committerLaurent Pinchart <laurent.pinchart@ideasonboard.com>2020-03-11 12:13:15 +0200
commite2769da7b70362c4e9ab0375a33d198d24795dbf (patch)
tree1d2722429877f84fcbd3f84d0e7bf476e0b81fe9
parent0e407303b5ab6c5c0b9db9dce46fd907debef170 (diff)
dt-bindings: phy: Add DT bindings for Xilinx ZynqMP PSGTR PHY
Add DT bindings for the Xilinx ZynqMP PHY. ZynqMP SoCs have a High Speed Processing System Gigabit Transceiver which provides PHY capabilities to USB, SATA, PCIE, Display Port and Ehernet SGMII controllers. Signed-off-by: Anurag Kumar Vulisha <anurag.kumar.vulisha@xilinx.com> Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> --- Changes since v5: - Document clocks and clock-names properties - Document resets and reset-names properties - Replace subnodes with an additional entry in the PHY cells - Drop lane frequency PHY cell, replaced by reference clock phandle - Convert bindings to YAML - Reword the subject line - Drop Rob's R-b as the bindings have significantly changed - Drop resets and reset-names properties
-rw-r--r--Documentation/devicetree/bindings/phy/xlnx,zynqmp-psgtr.yaml104
-rw-r--r--include/dt-bindings/phy/phy.h1
2 files changed, 105 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/phy/xlnx,zynqmp-psgtr.yaml b/Documentation/devicetree/bindings/phy/xlnx,zynqmp-psgtr.yaml
new file mode 100644
index 000000000000..9948e4a60e45
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/xlnx,zynqmp-psgtr.yaml
@@ -0,0 +1,104 @@
+# SPDX-License-Identifier: GPL-2.0
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/phy/xlnx,zynqmp-psgtr.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Xilinx ZynqMP Gigabit Transceiver PHY Device Tree Bindings
+
+maintainers:
+ - Laurent Pinchart <laurent.pinchart@ideasonboard.com>
+
+description: |
+ This binding describes the Xilinx ZynqMP Gigabit Transceiver (GTR) PHY. The
+ GTR provides four lanes and is used by USB, SATA, PCIE, Display port and
+ Ethernet SGMII controllers.
+
+properties:
+ "#phy-cells":
+ const: 4
+ description: |
+ The cells contain the following arguments.
+
+ - description: The GTR lane
+ minimum: 0
+ maximum: 3
+ - description: The PHY type
+ enum:
+ - PHY_TYPE_DP
+ - PHY_TYPE_PCIE
+ - PHY_TYPE_SATA
+ - PHY_TYPE_SGMII
+ - PHY_TYPE_USB
+ - description: The PHY instance
+ minimum: 0
+ maximum: 1 # for DP, SATA or USB
+ maximum: 3 # for PCIE or SGMII
+ - description: The reference clock number
+ minimum: 0
+ maximum: 3
+
+ compatible:
+ enum:
+ - xlnx,zynqmp-psgtr-v1.1
+ - xlnx,zynqmp-psgtr
+
+ clocks:
+ minItems: 1
+ maxItems: 4
+ description: |
+ Clock for each PS_MGTREFCLK[0-3] reference clock input. Unconnected
+ inputs shall not have an entry.
+
+ clock-names:
+ minItems: 1
+ maxItems: 4
+ items:
+ pattern: "^ref[0-3]$"
+
+ reg:
+ items:
+ - description: SERDES registers block
+ - description: SIOU registers block
+
+ reg-names:
+ items:
+ - const: serdes
+ - const: siou
+
+required:
+ - "#phy-cells"
+ - compatible
+ - reg
+ - reg-names
+
+if:
+ properties:
+ compatible:
+ const: xlnx,zynqmp-psgtr
+
+then:
+ properties:
+ xlnx,tx-termination-fix:
+ description: |
+ Include this for fixing functional issue with the TX termination
+ resistance in GT, which can be out of spec for the XCZU9EG silicon
+ version.
+ type: boolean
+
+additionalProperties: false
+
+examples:
+ - |
+ phy: phy@fd400000 {
+ compatible = "xlnx,zynqmp-psgtr-v1.1";
+ reg = <0x0 0xfd400000 0x0 0x40000>,
+ <0x0 0xfd3d0000 0x0 0x1000>;
+ reg-names = "serdes", "siou";
+ clocks = <&refclks 3>, <&refclks 2>, <&refclks 0>;
+ clock-names = "ref1", "ref2", "ref3";
+ #phy-cells = <4>;
+ status = "okay";
+ };
+
+...
diff --git a/include/dt-bindings/phy/phy.h b/include/dt-bindings/phy/phy.h
index 1f3f866fae7b..f6bc83b66ae9 100644
--- a/include/dt-bindings/phy/phy.h
+++ b/include/dt-bindings/phy/phy.h
@@ -17,5 +17,6 @@
#define PHY_TYPE_USB3 4
#define PHY_TYPE_UFS 5
#define PHY_TYPE_DP 6
+#define PHY_TYPE_SGMII 7
#endif /* _DT_BINDINGS_PHY */

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