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authorLaurent Pinchart <laurent.pinchart@ideasonboard.com>2019-09-06 01:15:32 +0300
committerLaurent Pinchart <laurent.pinchart@ideasonboard.com>2020-03-18 17:20:12 +0200
commit34fd58c751d8b02c1b2999817c1dd7faf6349192 (patch)
tree3c7fcd40e7724a32daf12173c87a4d148431ef8d
parentaab301ffff6d80e782037d45db294a05f7b4cff5 (diff)
arm64: dts: zynqmp: Add DisplayPort subsystem
Add a DT node for the DisplayPort subsystem, a hard IP present in the Zynq Ultrascale+ MPSoC. Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> --- Changes since v10: - Replace fixed frequency clocks with real clocks - Add resets property to zynqmp-dpsub Changes since v9: - Update to the latest DPDMA DT bindings
-rw-r--r--arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi6
-rw-r--r--arch/arm64/boot/dts/xilinx/zynqmp.dtsi24
2 files changed, 30 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi b/arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi
index 32c4914738d9..48db1b353a1a 100644
--- a/arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi
+++ b/arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi
@@ -61,6 +61,12 @@
clocks = <&zynqmp_clk DPDMA_REF>;
};
+&dpsub {
+ clocks = <&zynqmp_clk TOPSW_LSBUS>,
+ <&zynqmp_clk DP_AUDIO_REF>,
+ <&zynqmp_clk DP_VIDEO_REF>;
+};
+
&fpd_dma_chan1 {
clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;
};
diff --git a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi
index b195fd0dbeed..003fa5c4d572 100644
--- a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi
+++ b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi
@@ -12,6 +12,7 @@
* the License, or (at your option) any later version.
*/
+#include <dt-bindings/dma/xlnx-zynqmp-dpdma.h>
#include <dt-bindings/power/xlnx-zynqmp-power.h>
#include <dt-bindings/reset/xlnx-zynqmp-resets.h>
@@ -450,6 +451,29 @@
interrupts = <0 112 4>;
};
+ dpsub: display@fd4a0000 {
+ compatible = "xlnx,zynqmp-dpsub-1.7";
+ status = "disabled";
+ reg = <0x0 0xfd4a0000 0x0 0x1000>,
+ <0x0 0xfd4aa000 0x0 0x1000>,
+ <0x0 0xfd4ab000 0x0 0x1000>,
+ <0x0 0xfd4ac000 0x0 0x1000>;
+ reg-names = "dp", "blend", "av_buf", "aud";
+ interrupts = <0 119 4>;
+ interrupt-parent = <&gic>;
+
+ clock-names = "dp_apb_clk", "dp_aud_clk",
+ "dp_vtc_pixel_clk_in";
+
+ resets = <&reset ZYNQMP_RESET_DP>;
+
+ dma-names = "vid0", "vid1", "vid2", "gfx0";
+ dmas = <&dpdma ZYNQMP_DPDMA_VIDEO0>,
+ <&dpdma ZYNQMP_DPDMA_VIDEO1>,
+ <&dpdma ZYNQMP_DPDMA_VIDEO2>,
+ <&dpdma ZYNQMP_DPDMA_GRAPHICS>;
+ };
+
gem0: ethernet@ff0b0000 {
compatible = "cdns,zynqmp-gem", "cdns,gem";
status = "disabled";

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