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authorAlex Deucher <alexander.deucher@amd.com>2013-07-26 01:46:21 (GMT)
committerAlex Deucher <alexander.deucher@amd.com>2013-07-26 01:46:21 (GMT)
commitf5d9b7f0f93c6a7d40750b8b5528a1e0f0c678fb (patch)
treef698da963452568932f404cc329a96b2bf4d7e0e
parentf4f85a8c94752300ad2c4f7a3475a3d3b8ef72ca (diff)
drm/radeon/dpm: fix r600_enable_sclk_control()
Actually program the correct register to enable engine clock scaling control. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
-rw-r--r--drivers/gpu/drm/radeon/r600_dpm.c4
1 files changed, 2 insertions, 2 deletions
diff --git a/drivers/gpu/drm/radeon/r600_dpm.c b/drivers/gpu/drm/radeon/r600_dpm.c
index b88f54b..e5c860f 100644
--- a/drivers/gpu/drm/radeon/r600_dpm.c
+++ b/drivers/gpu/drm/radeon/r600_dpm.c
@@ -278,9 +278,9 @@ bool r600_dynamicpm_enabled(struct radeon_device *rdev)
void r600_enable_sclk_control(struct radeon_device *rdev, bool enable)
{
if (enable)
- WREG32_P(GENERAL_PWRMGT, 0, ~SCLK_PWRMGT_OFF);
+ WREG32_P(SCLK_PWRMGT_CNTL, 0, ~SCLK_PWRMGT_OFF);
else
- WREG32_P(GENERAL_PWRMGT, SCLK_PWRMGT_OFF, ~SCLK_PWRMGT_OFF);
+ WREG32_P(SCLK_PWRMGT_CNTL, SCLK_PWRMGT_OFF, ~SCLK_PWRMGT_OFF);
}
void r600_enable_mclk_control(struct radeon_device *rdev, bool enable)

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