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authorAaro Koskinen <aaro.koskinen@iki.fi>2013-06-06 22:34:56 +0300
committerGreg Kroah-Hartman <gregkh@linuxfoundation.org>2013-06-06 13:12:44 -0700
commita972c4830d4e7d566b3ce4304b037d5fe9ad2f5d (patch)
tree30d050ec3d198c1e34796f2345638f0280e03c2f /drivers/staging/octeon-usb
parent2dad6e4688bc7fecf50e6f895b84f3a0987b0af1 (diff)
staging: octeon-usb: cvmx-usbcx-defs.h: delete unused data types
Delete unused data types. Signed-off-by: Aaro Koskinen <aaro.koskinen@iki.fi> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Diffstat (limited to 'drivers/staging/octeon-usb')
-rw-r--r--drivers/staging/octeon-usb/cvmx-usbcx-defs.h1568
1 files changed, 0 insertions, 1568 deletions
diff --git a/drivers/staging/octeon-usb/cvmx-usbcx-defs.h b/drivers/staging/octeon-usb/cvmx-usbcx-defs.h
index e3ae545b725c..d3e779313131 100644
--- a/drivers/staging/octeon-usb/cvmx-usbcx-defs.h
+++ b/drivers/staging/octeon-usb/cvmx-usbcx-defs.h
@@ -106,1018 +106,6 @@
#define CVMX_USBCX_PCGCCTL(block_id) (CVMX_ADD_IO_SEG(0x00016F0010000E00ull) + ((block_id) & 1) * 0x100000000000ull)
/**
- * cvmx_usbc#_daint
- *
- * Device All Endpoints Interrupt Register (DAINT)
- *
- * When a significant event occurs on an endpoint, a Device All Endpoints Interrupt register
- * interrupts the application using the Device OUT Endpoints Interrupt bit or Device IN Endpoints
- * Interrupt bit of the Core Interrupt register (GINTSTS.OEPInt or GINTSTS.IEPInt, respectively).
- * There is one interrupt bit per endpoint, up to a maximum of 16 bits for OUT endpoints and 16
- * bits for IN endpoints. For a bidirectional endpoint, the corresponding IN and OUT interrupt
- * bits are used. Bits in this register are set and cleared when the application sets and clears
- * bits in the corresponding Device Endpoint-n Interrupt register (DIEPINTn/DOEPINTn).
- */
-union cvmx_usbcx_daint
-{
- uint32_t u32;
- struct cvmx_usbcx_daint_s
- {
- uint32_t outepint : 16; /**< OUT Endpoint Interrupt Bits (OutEPInt)
- One bit per OUT endpoint:
- Bit 16 for OUT endpoint 0, bit 31 for OUT endpoint 15 */
- uint32_t inepint : 16; /**< IN Endpoint Interrupt Bits (InEpInt)
- One bit per IN Endpoint:
- Bit 0 for IN endpoint 0, bit 15 for endpoint 15 */
- } s;
- struct cvmx_usbcx_daint_s cn30xx;
- struct cvmx_usbcx_daint_s cn31xx;
- struct cvmx_usbcx_daint_s cn50xx;
- struct cvmx_usbcx_daint_s cn52xx;
- struct cvmx_usbcx_daint_s cn52xxp1;
- struct cvmx_usbcx_daint_s cn56xx;
- struct cvmx_usbcx_daint_s cn56xxp1;
-};
-typedef union cvmx_usbcx_daint cvmx_usbcx_daint_t;
-
-/**
- * cvmx_usbc#_daintmsk
- *
- * Device All Endpoints Interrupt Mask Register (DAINTMSK)
- *
- * The Device Endpoint Interrupt Mask register works with the Device Endpoint Interrupt register
- * to interrupt the application when an event occurs on a device endpoint. However, the Device
- * All Endpoints Interrupt (DAINT) register bit corresponding to that interrupt will still be set.
- * Mask Interrupt: 1'b0 Unmask Interrupt: 1'b1
- */
-union cvmx_usbcx_daintmsk
-{
- uint32_t u32;
- struct cvmx_usbcx_daintmsk_s
- {
- uint32_t outepmsk : 16; /**< OUT EP Interrupt Mask Bits (OutEpMsk)
- One per OUT Endpoint:
- Bit 16 for OUT EP 0, bit 31 for OUT EP 15 */
- uint32_t inepmsk : 16; /**< IN EP Interrupt Mask Bits (InEpMsk)
- One bit per IN Endpoint:
- Bit 0 for IN EP 0, bit 15 for IN EP 15 */
- } s;
- struct cvmx_usbcx_daintmsk_s cn30xx;
- struct cvmx_usbcx_daintmsk_s cn31xx;
- struct cvmx_usbcx_daintmsk_s cn50xx;
- struct cvmx_usbcx_daintmsk_s cn52xx;
- struct cvmx_usbcx_daintmsk_s cn52xxp1;
- struct cvmx_usbcx_daintmsk_s cn56xx;
- struct cvmx_usbcx_daintmsk_s cn56xxp1;
-};
-typedef union cvmx_usbcx_daintmsk cvmx_usbcx_daintmsk_t;
-
-/**
- * cvmx_usbc#_dcfg
- *
- * Device Configuration Register (DCFG)
- *
- * This register configures the core in Device mode after power-on or after certain control
- * commands or enumeration. Do not make changes to this register after initial programming.
- */
-union cvmx_usbcx_dcfg
-{
- uint32_t u32;
- struct cvmx_usbcx_dcfg_s
- {
- uint32_t reserved_23_31 : 9;
- uint32_t epmiscnt : 5; /**< IN Endpoint Mismatch Count (EPMisCnt)
- The application programs this filed with a count that determines
- when the core generates an Endpoint Mismatch interrupt
- (GINTSTS.EPMis). The core loads this value into an internal
- counter and decrements it. The counter is reloaded whenever
- there is a match or when the counter expires. The width of this
- counter depends on the depth of the Token Queue. */
- uint32_t reserved_13_17 : 5;
- uint32_t perfrint : 2; /**< Periodic Frame Interval (PerFrInt)
- Indicates the time within a (micro)frame at which the application
- must be notified using the End Of Periodic Frame Interrupt. This
- can be used to determine if all the isochronous traffic for that
- (micro)frame is complete.
- * 2'b00: 80% of the (micro)frame interval
- * 2'b01: 85%
- * 2'b10: 90%
- * 2'b11: 95% */
- uint32_t devaddr : 7; /**< Device Address (DevAddr)
- The application must program this field after every SetAddress
- control command. */
- uint32_t reserved_3_3 : 1;
- uint32_t nzstsouthshk : 1; /**< Non-Zero-Length Status OUT Handshake (NZStsOUTHShk)
- The application can use this field to select the handshake the
- core sends on receiving a nonzero-length data packet during
- the OUT transaction of a control transfer's Status stage.
- * 1'b1: Send a STALL handshake on a nonzero-length status
- OUT transaction and do not send the received OUT packet to
- the application.
- * 1'b0: Send the received OUT packet to the application (zero-
- length or nonzero-length) and send a handshake based on
- the NAK and STALL bits for the endpoint in the Device
- Endpoint Control register. */
- uint32_t devspd : 2; /**< Device Speed (DevSpd)
- Indicates the speed at which the application requires the core to
- enumerate, or the maximum speed the application can support.
- However, the actual bus speed is determined only after the
- chirp sequence is completed, and is based on the speed of the
- USB host to which the core is connected. See "Device
- Initialization" on page 249 for details.
- * 2'b00: High speed (USB 2.0 PHY clock is 30 MHz or 60 MHz)
- * 2'b01: Full speed (USB 2.0 PHY clock is 30 MHz or 60 MHz)
- * 2'b10: Low speed (USB 1.1 transceiver clock is 6 MHz). If
- you select 6 MHz LS mode, you must do a soft reset.
- * 2'b11: Full speed (USB 1.1 transceiver clock is 48 MHz) */
- } s;
- struct cvmx_usbcx_dcfg_s cn30xx;
- struct cvmx_usbcx_dcfg_s cn31xx;
- struct cvmx_usbcx_dcfg_s cn50xx;
- struct cvmx_usbcx_dcfg_s cn52xx;
- struct cvmx_usbcx_dcfg_s cn52xxp1;
- struct cvmx_usbcx_dcfg_s cn56xx;
- struct cvmx_usbcx_dcfg_s cn56xxp1;
-};
-typedef union cvmx_usbcx_dcfg cvmx_usbcx_dcfg_t;
-
-/**
- * cvmx_usbc#_dctl
- *
- * Device Control Register (DCTL)
- *
- */
-union cvmx_usbcx_dctl
-{
- uint32_t u32;
- struct cvmx_usbcx_dctl_s
- {
- uint32_t reserved_12_31 : 20;
- uint32_t pwronprgdone : 1; /**< Power-On Programming Done (PWROnPrgDone)
- The application uses this bit to indicate that register
- programming is completed after a wake-up from Power Down
- mode. For more information, see "Device Mode Suspend and
- Resume With Partial Power-Down" on page 357. */
- uint32_t cgoutnak : 1; /**< Clear Global OUT NAK (CGOUTNak)
- A write to this field clears the Global OUT NAK. */
- uint32_t sgoutnak : 1; /**< Set Global OUT NAK (SGOUTNak)
- A write to this field sets the Global OUT NAK.
- The application uses this bit to send a NAK handshake on all
- OUT endpoints.
- The application should set the this bit only after making sure
- that the Global OUT NAK Effective bit in the Core Interrupt
- Register (GINTSTS.GOUTNakEff) is cleared. */
- uint32_t cgnpinnak : 1; /**< Clear Global Non-Periodic IN NAK (CGNPInNak)
- A write to this field clears the Global Non-Periodic IN NAK. */
- uint32_t sgnpinnak : 1; /**< Set Global Non-Periodic IN NAK (SGNPInNak)
- A write to this field sets the Global Non-Periodic IN NAK.The
- application uses this bit to send a NAK handshake on all non-
- periodic IN endpoints. The core can also set this bit when a
- timeout condition is detected on a non-periodic endpoint.
- The application should set this bit only after making sure that
- the Global IN NAK Effective bit in the Core Interrupt Register
- (GINTSTS.GINNakEff) is cleared. */
- uint32_t tstctl : 3; /**< Test Control (TstCtl)
- * 3'b000: Test mode disabled
- * 3'b001: Test_J mode
- * 3'b010: Test_K mode
- * 3'b011: Test_SE0_NAK mode
- * 3'b100: Test_Packet mode
- * 3'b101: Test_Force_Enable
- * Others: Reserved */
- uint32_t goutnaksts : 1; /**< Global OUT NAK Status (GOUTNakSts)
- * 1'b0: A handshake is sent based on the FIFO Status and the
- NAK and STALL bit settings.
- * 1'b1: No data is written to the RxFIFO, irrespective of space
- availability. Sends a NAK handshake on all packets, except
- on SETUP transactions. All isochronous OUT packets are
- dropped. */
- uint32_t gnpinnaksts : 1; /**< Global Non-Periodic IN NAK Status (GNPINNakSts)
- * 1'b0: A handshake is sent out based on the data availability
- in the transmit FIFO.
- * 1'b1: A NAK handshake is sent out on all non-periodic IN
- endpoints, irrespective of the data availability in the transmit
- FIFO. */
- uint32_t sftdiscon : 1; /**< Soft Disconnect (SftDiscon)
- The application uses this bit to signal the O2P USB core to do a
- soft disconnect. As long as this bit is set, the host will not see
- that the device is connected, and the device will not receive
- signals on the USB. The core stays in the disconnected state
- until the application clears this bit.
- The minimum duration for which the core must keep this bit set
- is specified in Minimum Duration for Soft Disconnect .
- * 1'b0: Normal operation. When this bit is cleared after a soft
- disconnect, the core drives the phy_opmode_o signal on the
- UTMI+ to 2'b00, which generates a device connect event to
- the USB host. When the device is reconnected, the USB host
- restarts device enumeration.
- * 1'b1: The core drives the phy_opmode_o signal on the
- UTMI+ to 2'b01, which generates a device disconnect event
- to the USB host. */
- uint32_t rmtwkupsig : 1; /**< Remote Wakeup Signaling (RmtWkUpSig)
- When the application sets this bit, the core initiates remote
- signaling to wake up the USB host.The application must set this
- bit to get the core out of Suspended state and must clear this bit
- after the core comes out of Suspended state. */
- } s;
- struct cvmx_usbcx_dctl_s cn30xx;
- struct cvmx_usbcx_dctl_s cn31xx;
- struct cvmx_usbcx_dctl_s cn50xx;
- struct cvmx_usbcx_dctl_s cn52xx;
- struct cvmx_usbcx_dctl_s cn52xxp1;
- struct cvmx_usbcx_dctl_s cn56xx;
- struct cvmx_usbcx_dctl_s cn56xxp1;
-};
-typedef union cvmx_usbcx_dctl cvmx_usbcx_dctl_t;
-
-/**
- * cvmx_usbc#_diepctl#
- *
- * Device IN Endpoint-n Control Register (DIEPCTLn)
- *
- * The application uses the register to control the behaviour of each logical endpoint other than endpoint 0.
- */
-union cvmx_usbcx_diepctlx
-{
- uint32_t u32;
- struct cvmx_usbcx_diepctlx_s
- {
- uint32_t epena : 1; /**< Endpoint Enable (EPEna)
- Indicates that data is ready to be transmitted on the endpoint.
- The core clears this bit before setting any of the following
- interrupts on this endpoint:
- * Endpoint Disabled
- * Transfer Completed */
- uint32_t epdis : 1; /**< Endpoint Disable (EPDis)
- The application sets this bit to stop transmitting data on an
- endpoint, even before the transfer for that endpoint is complete.
- The application must wait for the Endpoint Disabled interrupt
- before treating the endpoint as disabled. The core clears this bit
- before setting the Endpoint Disabled Interrupt. The application
- should set this bit only if Endpoint Enable is already set for this
- endpoint. */
- uint32_t setd1pid : 1; /**< For Interrupt/BULK enpoints:
- Set DATA1 PID (SetD1PID)
- Writing to this field sets the Endpoint Data Pid (DPID) field in
- this register to DATA1.
- For Isochronous endpoints:
- Set Odd (micro)frame (SetOddFr)
- Writing to this field sets the Even/Odd (micro)frame (EO_FrNum)
- field to odd (micro)frame. */
- uint32_t setd0pid : 1; /**< For Interrupt/BULK enpoints:
- Writing to this field sets the Endpoint Data Pid (DPID) field in
- this register to DATA0.
- For Isochronous endpoints:
- Set Odd (micro)frame (SetEvenFr)
- Writing to this field sets the Even/Odd (micro)frame (EO_FrNum)
- field to even (micro)frame. */
- uint32_t snak : 1; /**< Set NAK (SNAK)
- A write to this bit sets the NAK bit for the endpoint.
- Using this bit, the application can control the transmission of
- NAK handshakes on an endpoint. The core can also set this bit
- for an endpoint after a SETUP packet is received on the
- endpoint. */
- uint32_t cnak : 1; /**< Clear NAK (CNAK)
- A write to this bit clears the NAK bit for the endpoint. */
- uint32_t txfnum : 4; /**< TxFIFO Number (TxFNum)
- Non-periodic endpoints must set this bit to zero. Periodic
- endpoints must map this to the corresponding Periodic TxFIFO
- number.
- * 4'h0: Non-Periodic TxFIFO
- * Others: Specified Periodic TxFIFO number */
- uint32_t stall : 1; /**< STALL Handshake (Stall)
- For non-control, non-isochronous endpoints:
- The application sets this bit to stall all tokens from the USB host
- to this endpoint. If a NAK bit, Global Non-Periodic IN NAK, or
- Global OUT NAK is set along with this bit, the STALL bit takes
- priority. Only the application can clear this bit, never the core.
- For control endpoints:
- The application can only set this bit, and the core clears it, when
- a SETUP token i received for this endpoint. If a NAK bit, Global
- Non-Periodic IN NAK, or Global OUT NAK is set along with this
- bit, the STALL bit takes priority. Irrespective of this bit's setting,
- the core always responds to SETUP data packets with an ACK handshake. */
- uint32_t reserved_20_20 : 1;
- uint32_t eptype : 2; /**< Endpoint Type (EPType)
- This is the transfer type supported by this logical endpoint.
- * 2'b00: Control
- * 2'b01: Isochronous
- * 2'b10: Bulk
- * 2'b11: Interrupt */
- uint32_t naksts : 1; /**< NAK Status (NAKSts)
- Indicates the following:
- * 1'b0: The core is transmitting non-NAK handshakes based
- on the FIFO status
- * 1'b1: The core is transmitting NAK handshakes on this
- endpoint.
- When either the application or the core sets this bit:
- * For non-isochronous IN endpoints: The core stops
- transmitting any data on an IN endpoint, even if data is
- available in the TxFIFO.
- * For isochronous IN endpoints: The core sends out a zero-
- length data packet, even if data is available in the TxFIFO.
- Irrespective of this bit's setting, the core always responds to
- SETUP data packets with an ACK handshake. */
- uint32_t dpid : 1; /**< For interrupt/bulk IN and OUT endpoints:
- Endpoint Data PID (DPID)
- Contains the PID of the packet to be received or transmitted on
- this endpoint. The application should program the PID of the first
- packet to be received or transmitted on this endpoint, after the
- endpoint is activated. Applications use the SetD1PID and
- SetD0PID fields of this register to program either DATA0 or
- DATA1 PID.
- * 1'b0: DATA0
- * 1'b1: DATA1
- For isochronous IN and OUT endpoints:
- Even/Odd (Micro)Frame (EO_FrNum)
- Indicates the (micro)frame number in which the core transmits/
- receives isochronous data for this endpoint. The application
- should program the even/odd (micro) frame number in which it
- intends to transmit/receive isochronous data for this endpoint
- using the SetEvnFr and SetOddFr fields in this register.
- * 1'b0: Even (micro)frame
- * 1'b1: Odd (micro)frame */
- uint32_t usbactep : 1; /**< USB Active Endpoint (USBActEP)
- Indicates whether this endpoint is active in the current
- configuration and interface. The core clears this bit for all
- endpoints (other than EP 0) after detecting a USB reset. After
- receiving the SetConfiguration and SetInterface commands, the
- application must program endpoint registers accordingly and set
- this bit. */
- uint32_t nextep : 4; /**< Next Endpoint (NextEp)
- Applies to non-periodic IN endpoints only.
- Indicates the endpoint number to be fetched after the data for
- the current endpoint is fetched. The core can access this field,
- even when the Endpoint Enable (EPEna) bit is not set. This
- field is not valid in Slave mode. */
- uint32_t mps : 11; /**< Maximum Packet Size (MPS)
- Applies to IN and OUT endpoints.
- The application must program this field with the maximum
- packet size for the current logical endpoint. This value is in
- bytes. */
- } s;
- struct cvmx_usbcx_diepctlx_s cn30xx;
- struct cvmx_usbcx_diepctlx_s cn31xx;
- struct cvmx_usbcx_diepctlx_s cn50xx;
- struct cvmx_usbcx_diepctlx_s cn52xx;
- struct cvmx_usbcx_diepctlx_s cn52xxp1;
- struct cvmx_usbcx_diepctlx_s cn56xx;
- struct cvmx_usbcx_diepctlx_s cn56xxp1;
-};
-typedef union cvmx_usbcx_diepctlx cvmx_usbcx_diepctlx_t;
-
-/**
- * cvmx_usbc#_diepint#
- *
- * Device Endpoint-n Interrupt Register (DIEPINTn)
- *
- * This register indicates the status of an endpoint with respect to
- * USB- and AHB-related events. The application must read this register
- * when the OUT Endpoints Interrupt bit or IN Endpoints Interrupt bit of
- * the Core Interrupt register (GINTSTS.OEPInt or GINTSTS.IEPInt,
- * respectively) is set. Before the application can read this register,
- * it must first read the Device All Endpoints Interrupt (DAINT) register
- * to get the exact endpoint number for the Device Endpoint-n Interrupt
- * register. The application must clear the appropriate bit in this register
- * to clear the corresponding bits in the DAINT and GINTSTS registers.
- */
-union cvmx_usbcx_diepintx
-{
- uint32_t u32;
- struct cvmx_usbcx_diepintx_s
- {
- uint32_t reserved_7_31 : 25;
- uint32_t inepnakeff : 1; /**< IN Endpoint NAK Effective (INEPNakEff)
- Applies to periodic IN endpoints only.
- Indicates that the IN endpoint NAK bit set by the application has
- taken effect in the core. This bit can be cleared when the
- application clears the IN endpoint NAK by writing to
- DIEPCTLn.CNAK.
- This interrupt indicates that the core has sampled the NAK bit
- set (either by the application or by the core).
- This interrupt does not necessarily mean that a NAK handshake
- is sent on the USB. A STALL bit takes priority over a NAK bit. */
- uint32_t intknepmis : 1; /**< IN Token Received with EP Mismatch (INTknEPMis)
- Applies to non-periodic IN endpoints only.
- Indicates that the data in the top of the non-periodic TxFIFO
- belongs to an endpoint other than the one for which the IN
- token was received. This interrupt is asserted on the endpoint
- for which the IN token was received. */
- uint32_t intkntxfemp : 1; /**< IN Token Received When TxFIFO is Empty (INTknTXFEmp)
- Applies only to non-periodic IN endpoints.
- Indicates that an IN token was received when the associated
- TxFIFO (periodic/non-periodic) was empty. This interrupt is
- asserted on the endpoint for which the IN token was received. */
- uint32_t timeout : 1; /**< Timeout Condition (TimeOUT)
- Applies to non-isochronous IN endpoints only.
- Indicates that the core has detected a timeout condition on the
- USB for the last IN token on this endpoint. */
- uint32_t ahberr : 1; /**< AHB Error (AHBErr)
- This is generated only in Internal DMA mode when there is an
- AHB error during an AHB read/write. The application can read
- the corresponding endpoint DMA address register to get the
- error address. */
- uint32_t epdisbld : 1; /**< Endpoint Disabled Interrupt (EPDisbld)
- This bit indicates that the endpoint is disabled per the
- application's request. */
- uint32_t xfercompl : 1; /**< Transfer Completed Interrupt (XferCompl)
- Indicates that the programmed transfer is complete on the AHB
- as well as on the USB, for this endpoint. */
- } s;
- struct cvmx_usbcx_diepintx_s cn30xx;
- struct cvmx_usbcx_diepintx_s cn31xx;
- struct cvmx_usbcx_diepintx_s cn50xx;
- struct cvmx_usbcx_diepintx_s cn52xx;
- struct cvmx_usbcx_diepintx_s cn52xxp1;
- struct cvmx_usbcx_diepintx_s cn56xx;
- struct cvmx_usbcx_diepintx_s cn56xxp1;
-};
-typedef union cvmx_usbcx_diepintx cvmx_usbcx_diepintx_t;
-
-/**
- * cvmx_usbc#_diepmsk
- *
- * Device IN Endpoint Common Interrupt Mask Register (DIEPMSK)
- *
- * This register works with each of the Device IN Endpoint Interrupt (DIEPINTn) registers
- * for all endpoints to generate an interrupt per IN endpoint. The IN endpoint interrupt
- * for a specific status in the DIEPINTn register can be masked by writing to the corresponding
- * bit in this register. Status bits are masked by default.
- * Mask interrupt: 1'b0 Unmask interrupt: 1'b1
- */
-union cvmx_usbcx_diepmsk
-{
- uint32_t u32;
- struct cvmx_usbcx_diepmsk_s
- {
- uint32_t reserved_7_31 : 25;
- uint32_t inepnakeffmsk : 1; /**< IN Endpoint NAK Effective Mask (INEPNakEffMsk) */
- uint32_t intknepmismsk : 1; /**< IN Token received with EP Mismatch Mask (INTknEPMisMsk) */
- uint32_t intkntxfempmsk : 1; /**< IN Token Received When TxFIFO Empty Mask
- (INTknTXFEmpMsk) */
- uint32_t timeoutmsk : 1; /**< Timeout Condition Mask (TimeOUTMsk)
- (Non-isochronous endpoints) */
- uint32_t ahberrmsk : 1; /**< AHB Error Mask (AHBErrMsk) */
- uint32_t epdisbldmsk : 1; /**< Endpoint Disabled Interrupt Mask (EPDisbldMsk) */
- uint32_t xfercomplmsk : 1; /**< Transfer Completed Interrupt Mask (XferComplMsk) */
- } s;
- struct cvmx_usbcx_diepmsk_s cn30xx;
- struct cvmx_usbcx_diepmsk_s cn31xx;
- struct cvmx_usbcx_diepmsk_s cn50xx;
- struct cvmx_usbcx_diepmsk_s cn52xx;
- struct cvmx_usbcx_diepmsk_s cn52xxp1;
- struct cvmx_usbcx_diepmsk_s cn56xx;
- struct cvmx_usbcx_diepmsk_s cn56xxp1;
-};
-typedef union cvmx_usbcx_diepmsk cvmx_usbcx_diepmsk_t;
-
-/**
- * cvmx_usbc#_dieptsiz#
- *
- * Device Endpoint-n Transfer Size Register (DIEPTSIZn)
- *
- * The application must modify this register before enabling the endpoint.
- * Once the endpoint is enabled using Endpoint Enable bit of the Device Endpoint-n Control registers (DIEPCTLn.EPEna/DOEPCTLn.EPEna),
- * the core modifies this register. The application can only read this register once the core has cleared the Endpoint Enable bit.
- * This register is used only for endpoints other than Endpoint 0.
- */
-union cvmx_usbcx_dieptsizx
-{
- uint32_t u32;
- struct cvmx_usbcx_dieptsizx_s
- {
- uint32_t reserved_31_31 : 1;
- uint32_t mc : 2; /**< Multi Count (MC)
- Applies to IN endpoints only.
- For periodic IN endpoints, this field indicates the number of
- packets that must be transmitted per microframe on the USB.
- The core uses this field to calculate the data PID for
- isochronous IN endpoints.
- * 2'b01: 1 packet
- * 2'b10: 2 packets
- * 2'b11: 3 packets
- For non-periodic IN endpoints, this field is valid only in Internal
- DMA mode. It specifies the number of packets the core should
- fetch for an IN endpoint before it switches to the endpoint
- pointed to by the Next Endpoint field of the Device Endpoint-n
- Control register (DIEPCTLn.NextEp) */
- uint32_t pktcnt : 10; /**< Packet Count (PktCnt)
- Indicates the total number of USB packets that constitute the
- Transfer Size amount of data for this endpoint.
- IN Endpoints: This field is decremented every time a packet
- (maximum size or short packet) is read from the TxFIFO. */
- uint32_t xfersize : 19; /**< Transfer Size (XferSize)
- This field contains the transfer size in bytes for the current
- endpoint.
- The core only interrupts the application after it has exhausted
- the transfer size amount of data. The transfer size can be set to
- the maximum packet size of the endpoint, to be interrupted at
- the end of each packet.
- IN Endpoints: The core decrements this field every time a
- packet from the external memory is written to the TxFIFO. */
- } s;
- struct cvmx_usbcx_dieptsizx_s cn30xx;
- struct cvmx_usbcx_dieptsizx_s cn31xx;
- struct cvmx_usbcx_dieptsizx_s cn50xx;
- struct cvmx_usbcx_dieptsizx_s cn52xx;
- struct cvmx_usbcx_dieptsizx_s cn52xxp1;
- struct cvmx_usbcx_dieptsizx_s cn56xx;
- struct cvmx_usbcx_dieptsizx_s cn56xxp1;
-};
-typedef union cvmx_usbcx_dieptsizx cvmx_usbcx_dieptsizx_t;
-
-/**
- * cvmx_usbc#_doepctl#
- *
- * Device OUT Endpoint-n Control Register (DOEPCTLn)
- *
- * The application uses the register to control the behaviour of each logical endpoint other than endpoint 0.
- */
-union cvmx_usbcx_doepctlx
-{
- uint32_t u32;
- struct cvmx_usbcx_doepctlx_s
- {
- uint32_t epena : 1; /**< Endpoint Enable (EPEna)
- Indicates that the application has allocated the memory tp start
- receiving data from the USB.
- The core clears this bit before setting any of the following
- interrupts on this endpoint:
- * SETUP Phase Done
- * Endpoint Disabled
- * Transfer Completed
- For control OUT endpoints in DMA mode, this bit must be set
- to be able to transfer SETUP data packets in memory. */
- uint32_t epdis : 1; /**< Endpoint Disable (EPDis)
- The application sets this bit to stop transmitting data on an
- endpoint, even before the transfer for that endpoint is complete.
- The application must wait for the Endpoint Disabled interrupt
- before treating the endpoint as disabled. The core clears this bit
- before setting the Endpoint Disabled Interrupt. The application
- should set this bit only if Endpoint Enable is already set for this
- endpoint. */
- uint32_t setd1pid : 1; /**< For Interrupt/BULK enpoints:
- Set DATA1 PID (SetD1PID)
- Writing to this field sets the Endpoint Data Pid (DPID) field in
- this register to DATA1.
- For Isochronous endpoints:
- Set Odd (micro)frame (SetOddFr)
- Writing to this field sets the Even/Odd (micro)frame (EO_FrNum)
- field to odd (micro)frame. */
- uint32_t setd0pid : 1; /**< For Interrupt/BULK enpoints:
- Writing to this field sets the Endpoint Data Pid (DPID) field in
- this register to DATA0.
- For Isochronous endpoints:
- Set Odd (micro)frame (SetEvenFr)
- Writing to this field sets the Even/Odd (micro)frame (EO_FrNum)
- field to even (micro)frame. */
- uint32_t snak : 1; /**< Set NAK (SNAK)
- A write to this bit sets the NAK bit for the endpoint.
- Using this bit, the application can control the transmission of
- NAK handshakes on an endpoint. The core can also set this bit
- for an endpoint after a SETUP packet is received on the
- endpoint. */
- uint32_t cnak : 1; /**< Clear NAK (CNAK)
- A write to this bit clears the NAK bit for the endpoint. */
- uint32_t reserved_22_25 : 4;
- uint32_t stall : 1; /**< STALL Handshake (Stall)
- For non-control, non-isochronous endpoints:
- The application sets this bit to stall all tokens from the USB host
- to this endpoint. If a NAK bit, Global Non-Periodic IN NAK, or
- Global OUT NAK is set along with this bit, the STALL bit takes
- priority. Only the application can clear this bit, never the core.
- For control endpoints:
- The application can only set this bit, and the core clears it, when
- a SETUP token i received for this endpoint. If a NAK bit, Global
- Non-Periodic IN NAK, or Global OUT NAK is set along with this
- bit, the STALL bit takes priority. Irrespective of this bit's setting,
- the core always responds to SETUP data packets with an ACK handshake. */
- uint32_t snp : 1; /**< Snoop Mode (Snp)
- This bit configures the endpoint to Snoop mode. In Snoop mode,
- the core does not check the correctness of OUT packets before
- transferring them to application memory. */
- uint32_t eptype : 2; /**< Endpoint Type (EPType)
- This is the transfer type supported by this logical endpoint.
- * 2'b00: Control
- * 2'b01: Isochronous
- * 2'b10: Bulk
- * 2'b11: Interrupt */
- uint32_t naksts : 1; /**< NAK Status (NAKSts)
- Indicates the following:
- * 1'b0: The core is transmitting non-NAK handshakes based
- on the FIFO status
- * 1'b1: The core is transmitting NAK handshakes on this
- endpoint.
- When either the application or the core sets this bit:
- * The core stops receiving any data on an OUT endpoint, even
- if there is space in the RxFIFO to accomodate the incoming
- packet. */
- uint32_t dpid : 1; /**< For interrupt/bulk IN and OUT endpoints:
- Endpoint Data PID (DPID)
- Contains the PID of the packet to be received or transmitted on
- this endpoint. The application should program the PID of the first
- packet to be received or transmitted on this endpoint, after the
- endpoint is activated. Applications use the SetD1PID and
- SetD0PID fields of this register to program either DATA0 or
- DATA1 PID.
- * 1'b0: DATA0
- * 1'b1: DATA1
- For isochronous IN and OUT endpoints:
- Even/Odd (Micro)Frame (EO_FrNum)
- Indicates the (micro)frame number in which the core transmits/
- receives isochronous data for this endpoint. The application
- should program the even/odd (micro) frame number in which it
- intends to transmit/receive isochronous data for this endpoint
- using the SetEvnFr and SetOddFr fields in this register.
- * 1'b0: Even (micro)frame
- * 1'b1: Odd (micro)frame */
- uint32_t usbactep : 1; /**< USB Active Endpoint (USBActEP)
- Indicates whether this endpoint is active in the current
- configuration and interface. The core clears this bit for all
- endpoints (other than EP 0) after detecting a USB reset. After
- receiving the SetConfiguration and SetInterface commands, the
- application must program endpoint registers accordingly and set
- this bit. */
- uint32_t reserved_11_14 : 4;
- uint32_t mps : 11; /**< Maximum Packet Size (MPS)
- Applies to IN and OUT endpoints.
- The application must program this field with the maximum
- packet size for the current logical endpoint. This value is in
- bytes. */
- } s;
- struct cvmx_usbcx_doepctlx_s cn30xx;
- struct cvmx_usbcx_doepctlx_s cn31xx;
- struct cvmx_usbcx_doepctlx_s cn50xx;
- struct cvmx_usbcx_doepctlx_s cn52xx;
- struct cvmx_usbcx_doepctlx_s cn52xxp1;
- struct cvmx_usbcx_doepctlx_s cn56xx;
- struct cvmx_usbcx_doepctlx_s cn56xxp1;
-};
-typedef union cvmx_usbcx_doepctlx cvmx_usbcx_doepctlx_t;
-
-/**
- * cvmx_usbc#_doepint#
- *
- * Device Endpoint-n Interrupt Register (DOEPINTn)
- *
- * This register indicates the status of an endpoint with respect to USB- and AHB-related events.
- * The application must read this register when the OUT Endpoints Interrupt bit or IN Endpoints
- * Interrupt bit of the Core Interrupt register (GINTSTS.OEPInt or GINTSTS.IEPInt, respectively)
- * is set. Before the application can read this register, it must first read the Device All
- * Endpoints Interrupt (DAINT) register to get the exact endpoint number for the Device Endpoint-n
- * Interrupt register. The application must clear the appropriate bit in this register to clear the
- * corresponding bits in the DAINT and GINTSTS registers.
- */
-union cvmx_usbcx_doepintx
-{
- uint32_t u32;
- struct cvmx_usbcx_doepintx_s
- {
- uint32_t reserved_5_31 : 27;
- uint32_t outtknepdis : 1; /**< OUT Token Received When Endpoint Disabled (OUTTknEPdis)
- Applies only to control OUT endpoints.
- Indicates that an OUT token was received when the endpoint
- was not yet enabled. This interrupt is asserted on the endpoint
- for which the OUT token was received. */
- uint32_t setup : 1; /**< SETUP Phase Done (SetUp)
- Applies to control OUT endpoints only.
- Indicates that the SETUP phase for the control endpoint is
- complete and no more back-to-back SETUP packets were
- received for the current control transfer. On this interrupt, the
- application can decode the received SETUP data packet. */
- uint32_t ahberr : 1; /**< AHB Error (AHBErr)
- This is generated only in Internal DMA mode when there is an
- AHB error during an AHB read/write. The application can read
- the corresponding endpoint DMA address register to get the
- error address. */
- uint32_t epdisbld : 1; /**< Endpoint Disabled Interrupt (EPDisbld)
- This bit indicates that the endpoint is disabled per the
- application's request. */
- uint32_t xfercompl : 1; /**< Transfer Completed Interrupt (XferCompl)
- Indicates that the programmed transfer is complete on the AHB
- as well as on the USB, for this endpoint. */
- } s;
- struct cvmx_usbcx_doepintx_s cn30xx;
- struct cvmx_usbcx_doepintx_s cn31xx;
- struct cvmx_usbcx_doepintx_s cn50xx;
- struct cvmx_usbcx_doepintx_s cn52xx;
- struct cvmx_usbcx_doepintx_s cn52xxp1;
- struct cvmx_usbcx_doepintx_s cn56xx;
- struct cvmx_usbcx_doepintx_s cn56xxp1;
-};
-typedef union cvmx_usbcx_doepintx cvmx_usbcx_doepintx_t;
-
-/**
- * cvmx_usbc#_doepmsk
- *
- * Device OUT Endpoint Common Interrupt Mask Register (DOEPMSK)
- *
- * This register works with each of the Device OUT Endpoint Interrupt (DOEPINTn) registers
- * for all endpoints to generate an interrupt per OUT endpoint. The OUT endpoint interrupt
- * for a specific status in the DOEPINTn register can be masked by writing into the
- * corresponding bit in this register. Status bits are masked by default.
- * Mask interrupt: 1'b0 Unmask interrupt: 1'b1
- */
-union cvmx_usbcx_doepmsk
-{
- uint32_t u32;
- struct cvmx_usbcx_doepmsk_s
- {
- uint32_t reserved_5_31 : 27;
- uint32_t outtknepdismsk : 1; /**< OUT Token Received when Endpoint Disabled Mask
- (OUTTknEPdisMsk)
- Applies to control OUT endpoints only. */
- uint32_t setupmsk : 1; /**< SETUP Phase Done Mask (SetUPMsk)
- Applies to control endpoints only. */
- uint32_t ahberrmsk : 1; /**< AHB Error (AHBErrMsk) */
- uint32_t epdisbldmsk : 1; /**< Endpoint Disabled Interrupt Mask (EPDisbldMsk) */
- uint32_t xfercomplmsk : 1; /**< Transfer Completed Interrupt Mask (XferComplMsk) */
- } s;
- struct cvmx_usbcx_doepmsk_s cn30xx;
- struct cvmx_usbcx_doepmsk_s cn31xx;
- struct cvmx_usbcx_doepmsk_s cn50xx;
- struct cvmx_usbcx_doepmsk_s cn52xx;
- struct cvmx_usbcx_doepmsk_s cn52xxp1;
- struct cvmx_usbcx_doepmsk_s cn56xx;
- struct cvmx_usbcx_doepmsk_s cn56xxp1;
-};
-typedef union cvmx_usbcx_doepmsk cvmx_usbcx_doepmsk_t;
-
-/**
- * cvmx_usbc#_doeptsiz#
- *
- * Device Endpoint-n Transfer Size Register (DOEPTSIZn)
- *
- * The application must modify this register before enabling the endpoint.
- * Once the endpoint is enabled using Endpoint Enable bit of the Device Endpoint-n Control
- * registers (DOEPCTLn.EPEna/DOEPCTLn.EPEna), the core modifies this register. The application
- * can only read this register once the core has cleared the Endpoint Enable bit.
- * This register is used only for endpoints other than Endpoint 0.
- */
-union cvmx_usbcx_doeptsizx
-{
- uint32_t u32;
- struct cvmx_usbcx_doeptsizx_s
- {
- uint32_t reserved_31_31 : 1;
- uint32_t mc : 2; /**< Multi Count (MC)
- Received Data PID (RxDPID)
- Applies to isochronous OUT endpoints only.
- This is the data PID received in the last packet for this endpoint.
- 2'b00: DATA0
- 2'b01: DATA1
- 2'b10: DATA2
- 2'b11: MDATA
- SETUP Packet Count (SUPCnt)
- Applies to control OUT Endpoints only.
- This field specifies the number of back-to-back SETUP data
- packets the endpoint can receive.
- 2'b01: 1 packet
- 2'b10: 2 packets
- 2'b11: 3 packets */
- uint32_t pktcnt : 10; /**< Packet Count (PktCnt)
- Indicates the total number of USB packets that constitute the
- Transfer Size amount of data for this endpoint.
- OUT Endpoints: This field is decremented every time a
- packet (maximum size or short packet) is written to the
- RxFIFO. */
- uint32_t xfersize : 19; /**< Transfer Size (XferSize)
- This field contains the transfer size in bytes for the current
- endpoint.
- The core only interrupts the application after it has exhausted
- the transfer size amount of data. The transfer size can be set to
- the maximum packet size of the endpoint, to be interrupted at
- the end of each packet.
- OUT Endpoints: The core decrements this field every time a
- packet is read from the RxFIFO and written to the external
- memory. */
- } s;
- struct cvmx_usbcx_doeptsizx_s cn30xx;
- struct cvmx_usbcx_doeptsizx_s cn31xx;
- struct cvmx_usbcx_doeptsizx_s cn50xx;
- struct cvmx_usbcx_doeptsizx_s cn52xx;
- struct cvmx_usbcx_doeptsizx_s cn52xxp1;
- struct cvmx_usbcx_doeptsizx_s cn56xx;
- struct cvmx_usbcx_doeptsizx_s cn56xxp1;
-};
-typedef union cvmx_usbcx_doeptsizx cvmx_usbcx_doeptsizx_t;
-
-/**
- * cvmx_usbc#_dptxfsiz#
- *
- * Device Periodic Transmit FIFO-n Size Register (DPTXFSIZ)
- *
- * This register holds the memory start address of each periodic TxFIFO to implemented
- * in Device mode. Each periodic FIFO holds the data for one periodic IN endpoint.
- * This register is repeated for each periodic FIFO instantiated.
- */
-union cvmx_usbcx_dptxfsizx
-{
- uint32_t u32;
- struct cvmx_usbcx_dptxfsizx_s
- {
- uint32_t dptxfsize : 16; /**< Device Periodic TxFIFO Size (DPTxFSize)
- This value is in terms of 32-bit words.
- * Minimum value is 4
- * Maximum value is 768 */
- uint32_t dptxfstaddr : 16; /**< Device Periodic TxFIFO RAM Start Address (DPTxFStAddr)
- Holds the start address in the RAM for this periodic FIFO. */
- } s;
- struct cvmx_usbcx_dptxfsizx_s cn30xx;
- struct cvmx_usbcx_dptxfsizx_s cn31xx;
- struct cvmx_usbcx_dptxfsizx_s cn50xx;
- struct cvmx_usbcx_dptxfsizx_s cn52xx;
- struct cvmx_usbcx_dptxfsizx_s cn52xxp1;
- struct cvmx_usbcx_dptxfsizx_s cn56xx;
- struct cvmx_usbcx_dptxfsizx_s cn56xxp1;
-};
-typedef union cvmx_usbcx_dptxfsizx cvmx_usbcx_dptxfsizx_t;
-
-/**
- * cvmx_usbc#_dsts
- *
- * Device Status Register (DSTS)
- *
- * This register indicates the status of the core with respect to USB-related events.
- * It must be read on interrupts from Device All Interrupts (DAINT) register.
- */
-union cvmx_usbcx_dsts
-{
- uint32_t u32;
- struct cvmx_usbcx_dsts_s
- {
- uint32_t reserved_22_31 : 10;
- uint32_t soffn : 14; /**< Frame or Microframe Number of the Received SOF (SOFFN)
- When the core is operating at high speed, this field contains a
- microframe number. When the core is operating at full or low
- speed, this field contains a frame number. */
- uint32_t reserved_4_7 : 4;
- uint32_t errticerr : 1; /**< Erratic Error (ErrticErr)
- The core sets this bit to report any erratic errors
- (phy_rxvalid_i/phy_rxvldh_i or phy_rxactive_i is asserted for at
- least 2 ms, due to PHY error) seen on the UTMI+.
- Due to erratic errors, the O2P USB core goes into Suspended
- state and an interrupt is generated to the application with Early
- Suspend bit of the Core Interrupt register (GINTSTS.ErlySusp).
- If the early suspend is asserted due to an erratic error, the
- application can only perform a soft disconnect recover. */
- uint32_t enumspd : 2; /**< Enumerated Speed (EnumSpd)
- Indicates the speed at which the O2P USB core has come up
- after speed detection through a chirp sequence.
- * 2'b00: High speed (PHY clock is running at 30 or 60 MHz)
- * 2'b01: Full speed (PHY clock is running at 30 or 60 MHz)
- * 2'b10: Low speed (PHY clock is running at 6 MHz)
- * 2'b11: Full speed (PHY clock is running at 48 MHz)
- Low speed is not supported for devices using a UTMI+ PHY. */
- uint32_t suspsts : 1; /**< Suspend Status (SuspSts)
- In Device mode, this bit is set as long as a Suspend condition is
- detected on the USB. The core enters the Suspended state
- when there is no activity on the phy_line_state_i signal for an
- extended period of time. The core comes out of the suspend:
- * When there is any activity on the phy_line_state_i signal
- * When the application writes to the Remote Wakeup Signaling
- bit in the Device Control register (DCTL.RmtWkUpSig). */
- } s;
- struct cvmx_usbcx_dsts_s cn30xx;
- struct cvmx_usbcx_dsts_s cn31xx;
- struct cvmx_usbcx_dsts_s cn50xx;
- struct cvmx_usbcx_dsts_s cn52xx;
- struct cvmx_usbcx_dsts_s cn52xxp1;
- struct cvmx_usbcx_dsts_s cn56xx;
- struct cvmx_usbcx_dsts_s cn56xxp1;
-};
-typedef union cvmx_usbcx_dsts cvmx_usbcx_dsts_t;
-
-/**
- * cvmx_usbc#_dtknqr1
- *
- * Device IN Token Sequence Learning Queue Read Register 1 (DTKNQR1)
- *
- * The depth of the IN Token Sequence Learning Queue is specified for Device Mode IN Token
- * Sequence Learning Queue Depth. The queue is 4 bits wide to store the endpoint number.
- * A read from this register returns the first 5 endpoint entries of the IN Token Sequence
- * Learning Queue. When the queue is full, the new token is pushed into the queue and oldest
- * token is discarded.
- */
-union cvmx_usbcx_dtknqr1
-{
- uint32_t u32;
- struct cvmx_usbcx_dtknqr1_s
- {
- uint32_t eptkn : 24; /**< Endpoint Token (EPTkn)
- Four bits per token represent the endpoint number of the token:
- * Bits [31:28]: Endpoint number of Token 5
- * Bits [27:24]: Endpoint number of Token 4
- - .......
- * Bits [15:12]: Endpoint number of Token 1
- * Bits [11:8]: Endpoint number of Token 0 */
- uint32_t wrapbit : 1; /**< Wrap Bit (WrapBit)
- This bit is set when the write pointer wraps. It is cleared when
- the learning queue is cleared. */
- uint32_t reserved_5_6 : 2;
- uint32_t intknwptr : 5; /**< IN Token Queue Write Pointer (INTknWPtr) */
- } s;
- struct cvmx_usbcx_dtknqr1_s cn30xx;
- struct cvmx_usbcx_dtknqr1_s cn31xx;
- struct cvmx_usbcx_dtknqr1_s cn50xx;
- struct cvmx_usbcx_dtknqr1_s cn52xx;
- struct cvmx_usbcx_dtknqr1_s cn52xxp1;
- struct cvmx_usbcx_dtknqr1_s cn56xx;
- struct cvmx_usbcx_dtknqr1_s cn56xxp1;
-};
-typedef union cvmx_usbcx_dtknqr1 cvmx_usbcx_dtknqr1_t;
-
-/**
- * cvmx_usbc#_dtknqr2
- *
- * Device IN Token Sequence Learning Queue Read Register 2 (DTKNQR2)
- *
- * A read from this register returns the next 8 endpoint entries of the learning queue.
- */
-union cvmx_usbcx_dtknqr2
-{
- uint32_t u32;
- struct cvmx_usbcx_dtknqr2_s
- {
- uint32_t eptkn : 32; /**< Endpoint Token (EPTkn)
- Four bits per token represent the endpoint number of the token:
- * Bits [31:28]: Endpoint number of Token 13
- * Bits [27:24]: Endpoint number of Token 12
- - .......
- * Bits [7:4]: Endpoint number of Token 7
- * Bits [3:0]: Endpoint number of Token 6 */
- } s;
- struct cvmx_usbcx_dtknqr2_s cn30xx;
- struct cvmx_usbcx_dtknqr2_s cn31xx;
- struct cvmx_usbcx_dtknqr2_s cn50xx;
- struct cvmx_usbcx_dtknqr2_s cn52xx;
- struct cvmx_usbcx_dtknqr2_s cn52xxp1;
- struct cvmx_usbcx_dtknqr2_s cn56xx;
- struct cvmx_usbcx_dtknqr2_s cn56xxp1;
-};
-typedef union cvmx_usbcx_dtknqr2 cvmx_usbcx_dtknqr2_t;
-
-/**
- * cvmx_usbc#_dtknqr3
- *
- * Device IN Token Sequence Learning Queue Read Register 3 (DTKNQR3)
- *
- * A read from this register returns the next 8 endpoint entries of the learning queue.
- */
-union cvmx_usbcx_dtknqr3
-{
- uint32_t u32;
- struct cvmx_usbcx_dtknqr3_s
- {
- uint32_t eptkn : 32; /**< Endpoint Token (EPTkn)
- Four bits per token represent the endpoint number of the token:
- * Bits [31:28]: Endpoint number of Token 21
- * Bits [27:24]: Endpoint number of Token 20
- - .......
- * Bits [7:4]: Endpoint number of Token 15
- * Bits [3:0]: Endpoint number of Token 14 */
- } s;
- struct cvmx_usbcx_dtknqr3_s cn30xx;
- struct cvmx_usbcx_dtknqr3_s cn31xx;
- struct cvmx_usbcx_dtknqr3_s cn50xx;
- struct cvmx_usbcx_dtknqr3_s cn52xx;
- struct cvmx_usbcx_dtknqr3_s cn52xxp1;
- struct cvmx_usbcx_dtknqr3_s cn56xx;
- struct cvmx_usbcx_dtknqr3_s cn56xxp1;
-};
-typedef union cvmx_usbcx_dtknqr3 cvmx_usbcx_dtknqr3_t;
-
-/**
- * cvmx_usbc#_dtknqr4
- *
- * Device IN Token Sequence Learning Queue Read Register 4 (DTKNQR4)
- *
- * A read from this register returns the last 8 endpoint entries of the learning queue.
- */
-union cvmx_usbcx_dtknqr4
-{
- uint32_t u32;
- struct cvmx_usbcx_dtknqr4_s
- {
- uint32_t eptkn : 32; /**< Endpoint Token (EPTkn)
- Four bits per token represent the endpoint number of the token:
- * Bits [31:28]: Endpoint number of Token 29
- * Bits [27:24]: Endpoint number of Token 28
- - .......
- * Bits [7:4]: Endpoint number of Token 23
- * Bits [3:0]: Endpoint number of Token 22 */
- } s;
- struct cvmx_usbcx_dtknqr4_s cn30xx;
- struct cvmx_usbcx_dtknqr4_s cn31xx;
- struct cvmx_usbcx_dtknqr4_s cn50xx;
- struct cvmx_usbcx_dtknqr4_s cn52xx;
- struct cvmx_usbcx_dtknqr4_s cn52xxp1;
- struct cvmx_usbcx_dtknqr4_s cn56xx;
- struct cvmx_usbcx_dtknqr4_s cn56xxp1;
-};
-typedef union cvmx_usbcx_dtknqr4 cvmx_usbcx_dtknqr4_t;
-
-/**
* cvmx_usbc#_gahbcfg
*
* Core AHB Configuration Register (GAHBCFG)
@@ -1179,121 +167,6 @@ union cvmx_usbcx_gahbcfg
typedef union cvmx_usbcx_gahbcfg cvmx_usbcx_gahbcfg_t;
/**
- * cvmx_usbc#_ghwcfg1
- *
- * User HW Config1 Register (GHWCFG1)
- *
- * This register contains the logical endpoint direction(s) of the O2P USB core.
- */
-union cvmx_usbcx_ghwcfg1
-{
- uint32_t u32;
- struct cvmx_usbcx_ghwcfg1_s
- {
- uint32_t epdir : 32; /**< Endpoint Direction (epdir)
- Two bits per endpoint represent the direction.
- * 2'b00: BIDIR (IN and OUT) endpoint
- * 2'b01: IN endpoint
- * 2'b10: OUT endpoint
- * 2'b11: Reserved
- Bits [31:30]: Endpoint 15 direction
- Bits [29:28]: Endpoint 14 direction
- - ...
- Bits [3:2]: Endpoint 1 direction
- Bits[1:0]: Endpoint 0 direction (always BIDIR) */
- } s;
- struct cvmx_usbcx_ghwcfg1_s cn30xx;
- struct cvmx_usbcx_ghwcfg1_s cn31xx;
- struct cvmx_usbcx_ghwcfg1_s cn50xx;
- struct cvmx_usbcx_ghwcfg1_s cn52xx;
- struct cvmx_usbcx_ghwcfg1_s cn52xxp1;
- struct cvmx_usbcx_ghwcfg1_s cn56xx;
- struct cvmx_usbcx_ghwcfg1_s cn56xxp1;
-};
-typedef union cvmx_usbcx_ghwcfg1 cvmx_usbcx_ghwcfg1_t;
-
-/**
- * cvmx_usbc#_ghwcfg2
- *
- * User HW Config2 Register (GHWCFG2)
- *
- * This register contains configuration options of the O2P USB core.
- */
-union cvmx_usbcx_ghwcfg2
-{
- uint32_t u32;
- struct cvmx_usbcx_ghwcfg2_s
- {
- uint32_t reserved_31_31 : 1;
- uint32_t tknqdepth : 5; /**< Device Mode IN Token Sequence Learning Queue Depth
- (TknQDepth)
- Range: 0-30 */
- uint32_t ptxqdepth : 2; /**< Host Mode Periodic Request Queue Depth (PTxQDepth)
- * 2'b00: 2
- * 2'b01: 4
- * 2'b10: 8
- * Others: Reserved */
- uint32_t nptxqdepth : 2; /**< Non-Periodic Request Queue Depth (NPTxQDepth)
- * 2'b00: 2
- * 2'b01: 4
- * 2'b10: 8
- * Others: Reserved */
- uint32_t reserved_20_21 : 2;
- uint32_t dynfifosizing : 1; /**< Dynamic FIFO Sizing Enabled (DynFifoSizing)
- * 1'b0: No
- * 1'b1: Yes */
- uint32_t periosupport : 1; /**< Periodic OUT Channels Supported in Host Mode
- (PerioSupport)
- * 1'b0: No
- * 1'b1: Yes */
- uint32_t numhstchnl : 4; /**< Number of Host Channels (NumHstChnl)
- Indicates the number of host channels supported by the core in
- Host mode. The range of this field is 0-15: 0 specifies 1
- channel, 15 specifies 16 channels. */
- uint32_t numdeveps : 4; /**< Number of Device Endpoints (NumDevEps)
- Indicates the number of device endpoints supported by the core
- in Device mode in addition to control endpoint 0. The range of
- this field is 1-15. */
- uint32_t fsphytype : 2; /**< Full-Speed PHY Interface Type (FSPhyType)
- * 2'b00: Full-speed interface not supported
- * 2'b01: Dedicated full-speed interface
- * 2'b10: FS pins shared with UTMI+ pins
- * 2'b11: FS pins shared with ULPI pins */
- uint32_t hsphytype : 2; /**< High-Speed PHY Interface Type (HSPhyType)
- * 2'b00: High-Speed interface not supported
- * 2'b01: UTMI+
- * 2'b10: ULPI
- * 2'b11: UTMI+ and ULPI */
- uint32_t singpnt : 1; /**< Point-to-Point (SingPnt)
- * 1'b0: Multi-point application
- * 1'b1: Single-point application */
- uint32_t otgarch : 2; /**< Architecture (OtgArch)
- * 2'b00: Slave-Only
- * 2'b01: External DMA
- * 2'b10: Internal DMA
- * Others: Reserved */
- uint32_t otgmode : 3; /**< Mode of Operation (OtgMode)
- * 3'b000: HNP- and SRP-Capable OTG (Host & Device)
- * 3'b001: SRP-Capable OTG (Host & Device)
- * 3'b010: Non-HNP and Non-SRP Capable OTG (Host &
- Device)
- * 3'b011: SRP-Capable Device
- * 3'b100: Non-OTG Device
- * 3'b101: SRP-Capable Host
- * 3'b110: Non-OTG Host
- * Others: Reserved */
- } s;
- struct cvmx_usbcx_ghwcfg2_s cn30xx;
- struct cvmx_usbcx_ghwcfg2_s cn31xx;
- struct cvmx_usbcx_ghwcfg2_s cn50xx;
- struct cvmx_usbcx_ghwcfg2_s cn52xx;
- struct cvmx_usbcx_ghwcfg2_s cn52xxp1;
- struct cvmx_usbcx_ghwcfg2_s cn56xx;
- struct cvmx_usbcx_ghwcfg2_s cn56xxp1;
-};
-typedef union cvmx_usbcx_ghwcfg2 cvmx_usbcx_ghwcfg2_t;
-
-/**
* cvmx_usbc#_ghwcfg3
*
* User HW Config3 Register (GHWCFG3)
@@ -1361,107 +234,6 @@ union cvmx_usbcx_ghwcfg3
typedef union cvmx_usbcx_ghwcfg3 cvmx_usbcx_ghwcfg3_t;
/**
- * cvmx_usbc#_ghwcfg4
- *
- * User HW Config4 Register (GHWCFG4)
- *
- * This register contains the configuration options of the O2P USB core.
- */
-union cvmx_usbcx_ghwcfg4
-{
- uint32_t u32;
- struct cvmx_usbcx_ghwcfg4_s
- {
- uint32_t reserved_30_31 : 2;
- uint32_t numdevmodinend : 4; /**< Enable dedicatd transmit FIFO for device IN endpoints. */
- uint32_t endedtrfifo : 1; /**< Enable dedicatd transmit FIFO for device IN endpoints. */
- uint32_t sessendfltr : 1; /**< "session_end" Filter Enabled (SessEndFltr)
- * 1'b0: No filter
- * 1'b1: Filter */
- uint32_t bvalidfltr : 1; /**< "b_valid" Filter Enabled (BValidFltr)
- * 1'b0: No filter
- * 1'b1: Filter */
- uint32_t avalidfltr : 1; /**< "a_valid" Filter Enabled (AValidFltr)
- * 1'b0: No filter
- * 1'b1: Filter */
- uint32_t vbusvalidfltr : 1; /**< "vbus_valid" Filter Enabled (VBusValidFltr)
- * 1'b0: No filter
- * 1'b1: Filter */
- uint32_t iddgfltr : 1; /**< "iddig" Filter Enable (IddgFltr)
- * 1'b0: No filter
- * 1'b1: Filter */
- uint32_t numctleps : 4; /**< Number of Device Mode Control Endpoints in Addition to
- Endpoint 0 (NumCtlEps)
- Range: 1-15 */
- uint32_t phydatawidth : 2; /**< UTMI+ PHY/ULPI-to-Internal UTMI+ Wrapper Data Width
- (PhyDataWidth)
- When a ULPI PHY is used, an internal wrapper converts ULPI
- to UTMI+.
- * 2'b00: 8 bits
- * 2'b01: 16 bits
- * 2'b10: 8/16 bits, software selectable
- * Others: Reserved */
- uint32_t reserved_6_13 : 8;
- uint32_t ahbfreq : 1; /**< Minimum AHB Frequency Less Than 60 MHz (AhbFreq)
- * 1'b0: No
- * 1'b1: Yes */
- uint32_t enablepwropt : 1; /**< Enable Power Optimization? (EnablePwrOpt)
- * 1'b0: No
- * 1'b1: Yes */
- uint32_t numdevperioeps : 4; /**< Number of Device Mode Periodic IN Endpoints
- (NumDevPerioEps)
- Range: 0-15 */
- } s;
- struct cvmx_usbcx_ghwcfg4_cn30xx
- {
- uint32_t reserved_25_31 : 7;
- uint32_t sessendfltr : 1; /**< "session_end" Filter Enabled (SessEndFltr)
- * 1'b0: No filter
- * 1'b1: Filter */
- uint32_t bvalidfltr : 1; /**< "b_valid" Filter Enabled (BValidFltr)
- * 1'b0: No filter
- * 1'b1: Filter */
- uint32_t avalidfltr : 1; /**< "a_valid" Filter Enabled (AValidFltr)
- * 1'b0: No filter
- * 1'b1: Filter */
- uint32_t vbusvalidfltr : 1; /**< "vbus_valid" Filter Enabled (VBusValidFltr)
- * 1'b0: No filter
- * 1'b1: Filter */
- uint32_t iddgfltr : 1; /**< "iddig" Filter Enable (IddgFltr)
- * 1'b0: No filter
- * 1'b1: Filter */
- uint32_t numctleps : 4; /**< Number of Device Mode Control Endpoints in Addition to
- Endpoint 0 (NumCtlEps)
- Range: 1-15 */
- uint32_t phydatawidth : 2; /**< UTMI+ PHY/ULPI-to-Internal UTMI+ Wrapper Data Width
- (PhyDataWidth)
- When a ULPI PHY is used, an internal wrapper converts ULPI
- to UTMI+.
- * 2'b00: 8 bits
- * 2'b01: 16 bits
- * 2'b10: 8/16 bits, software selectable
- * Others: Reserved */
- uint32_t reserved_6_13 : 8;
- uint32_t ahbfreq : 1; /**< Minimum AHB Frequency Less Than 60 MHz (AhbFreq)
- * 1'b0: No
- * 1'b1: Yes */
- uint32_t enablepwropt : 1; /**< Enable Power Optimization? (EnablePwrOpt)
- * 1'b0: No
- * 1'b1: Yes */
- uint32_t numdevperioeps : 4; /**< Number of Device Mode Periodic IN Endpoints
- (NumDevPerioEps)
- Range: 0-15 */
- } cn30xx;
- struct cvmx_usbcx_ghwcfg4_cn30xx cn31xx;
- struct cvmx_usbcx_ghwcfg4_s cn50xx;
- struct cvmx_usbcx_ghwcfg4_s cn52xx;
- struct cvmx_usbcx_ghwcfg4_s cn52xxp1;
- struct cvmx_usbcx_ghwcfg4_s cn56xx;
- struct cvmx_usbcx_ghwcfg4_s cn56xxp1;
-};
-typedef union cvmx_usbcx_ghwcfg4 cvmx_usbcx_ghwcfg4_t;
-
-/**
* cvmx_usbc#_gintmsk
*
* Core Interrupt Mask Register (GINTMSK)
@@ -1814,100 +586,6 @@ union cvmx_usbcx_gnptxsts
typedef union cvmx_usbcx_gnptxsts cvmx_usbcx_gnptxsts_t;
/**
- * cvmx_usbc#_gotgctl
- *
- * OTG Control and Status Register (GOTGCTL)
- *
- * The OTG Control and Status register controls the behavior and reflects the status of the OTG function of the core.:
- */
-union cvmx_usbcx_gotgctl
-{
- uint32_t u32;
- struct cvmx_usbcx_gotgctl_s
- {
- uint32_t reserved_20_31 : 12;
- uint32_t bsesvld : 1; /**< B-Session Valid (BSesVld)
- Valid only when O2P USB core is configured as a USB device.
- Indicates the Device mode transceiver status.
- * 1'b0: B-session is not valid.
- * 1'b1: B-session is valid. */
- uint32_t asesvld : 1; /**< A-Session Valid (ASesVld)
- Valid only when O2P USB core is configured as a USB host.
- Indicates the Host mode transceiver status.
- * 1'b0: A-session is not valid
- * 1'b1: A-session is valid */
- uint32_t dbnctime : 1; /**< Long/Short Debounce Time (DbncTime)
- In the present version of the core this bit will only read as '0'. */
- uint32_t conidsts : 1; /**< Connector ID Status (ConIDSts)
- Indicates the connector ID status on a connect event.
- * 1'b0: The O2P USB core is in A-device mode
- * 1'b1: The O2P USB core is in B-device mode */
- uint32_t reserved_12_15 : 4;
- uint32_t devhnpen : 1; /**< Device HNP Enabled (DevHNPEn)
- Since O2P USB core is not HNP capable this bit is 0x0. */
- uint32_t hstsethnpen : 1; /**< Host Set HNP Enable (HstSetHNPEn)
- Since O2P USB core is not HNP capable this bit is 0x0. */
- uint32_t hnpreq : 1; /**< HNP Request (HNPReq)
- Since O2P USB core is not HNP capable this bit is 0x0. */
- uint32_t hstnegscs : 1; /**< Host Negotiation Success (HstNegScs)
- Since O2P USB core is not HNP capable this bit is 0x0. */
- uint32_t reserved_2_7 : 6;
- uint32_t sesreq : 1; /**< Session Request (SesReq)
- Since O2P USB core is not SRP capable this bit is 0x0. */
- uint32_t sesreqscs : 1; /**< Session Request Success (SesReqScs)
- Since O2P USB core is not SRP capable this bit is 0x0. */
- } s;
- struct cvmx_usbcx_gotgctl_s cn30xx;
- struct cvmx_usbcx_gotgctl_s cn31xx;
- struct cvmx_usbcx_gotgctl_s cn50xx;
- struct cvmx_usbcx_gotgctl_s cn52xx;
- struct cvmx_usbcx_gotgctl_s cn52xxp1;
- struct cvmx_usbcx_gotgctl_s cn56xx;
- struct cvmx_usbcx_gotgctl_s cn56xxp1;
-};
-typedef union cvmx_usbcx_gotgctl cvmx_usbcx_gotgctl_t;
-
-/**
- * cvmx_usbc#_gotgint
- *
- * OTG Interrupt Register (GOTGINT)
- *
- * The application reads this register whenever there is an OTG interrupt and clears the bits in this register
- * to clear the OTG interrupt. It is shown in Interrupt .:
- */
-union cvmx_usbcx_gotgint
-{
- uint32_t u32;
- struct cvmx_usbcx_gotgint_s
- {
- uint32_t reserved_20_31 : 12;
- uint32_t dbncedone : 1; /**< Debounce Done (DbnceDone)
- In the present version of the code this bit is tied to '0'. */
- uint32_t adevtoutchg : 1; /**< A-Device Timeout Change (ADevTOUTChg)
- Since O2P USB core is not HNP or SRP capable this bit is always 0x0. */
- uint32_t hstnegdet : 1; /**< Host Negotiation Detected (HstNegDet)
- Since O2P USB core is not HNP or SRP capable this bit is always 0x0. */
- uint32_t reserved_10_16 : 7;
- uint32_t hstnegsucstschng : 1; /**< Host Negotiation Success Status Change (HstNegSucStsChng)
- Since O2P USB core is not HNP or SRP capable this bit is always 0x0. */
- uint32_t sesreqsucstschng : 1; /**< Session Request Success Status Change
- Since O2P USB core is not HNP or SRP capable this bit is always 0x0. */
- uint32_t reserved_3_7 : 5;
- uint32_t sesenddet : 1; /**< Session End Detected (SesEndDet)
- Since O2P USB core is not HNP or SRP capable this bit is always 0x0. */
- uint32_t reserved_0_1 : 2;
- } s;
- struct cvmx_usbcx_gotgint_s cn30xx;
- struct cvmx_usbcx_gotgint_s cn31xx;
- struct cvmx_usbcx_gotgint_s cn50xx;
- struct cvmx_usbcx_gotgint_s cn52xx;
- struct cvmx_usbcx_gotgint_s cn52xxp1;
- struct cvmx_usbcx_gotgint_s cn56xx;
- struct cvmx_usbcx_gotgint_s cn56xxp1;
-};
-typedef union cvmx_usbcx_gotgint cvmx_usbcx_gotgint_t;
-
-/**
* cvmx_usbc#_grstctl
*
* Core Reset Register (GRSTCTL)
@@ -2060,55 +738,6 @@ union cvmx_usbcx_grxfsiz
typedef union cvmx_usbcx_grxfsiz cvmx_usbcx_grxfsiz_t;
/**
- * cvmx_usbc#_grxstspd
- *
- * Receive Status Debug Read Register, Device Mode (GRXSTSPD)
- *
- * A read to the Receive Status Read and Pop register returns and additionally pops the top data entry out of the RxFIFO.
- * This Description is only valid when the core is in Device Mode. For Host Mode use USBC_GRXSTSPH instead.
- * NOTE: GRXSTSPH and GRXSTSPD are physically the same register and share the same offset in the O2P USB core.
- * The offset difference shown in this document is for software clarity and is actually ignored by the
- * hardware.
- */
-union cvmx_usbcx_grxstspd
-{
- uint32_t u32;
- struct cvmx_usbcx_grxstspd_s
- {
- uint32_t reserved_25_31 : 7;
- uint32_t fn : 4; /**< Frame Number (FN)
- This is the least significant 4 bits of the (micro)frame number in
- which the packet is received on the USB. This field is supported
- only when the isochronous OUT endpoints are supported. */
- uint32_t pktsts : 4; /**< Packet Status (PktSts)
- Indicates the status of the received packet
- * 4'b0001: Glogal OUT NAK (triggers an interrupt)
- * 4'b0010: OUT data packet received
- * 4'b0100: SETUP transaction completed (triggers an interrupt)
- * 4'b0110: SETUP data packet received
- * Others: Reserved */
- uint32_t dpid : 2; /**< Data PID (DPID)
- * 2'b00: DATA0
- * 2'b10: DATA1
- * 2'b01: DATA2
- * 2'b11: MDATA */
- uint32_t bcnt : 11; /**< Byte Count (BCnt)
- Indicates the byte count of the received data packet */
- uint32_t epnum : 4; /**< Endpoint Number (EPNum)
- Indicates the endpoint number to which the current received
- packet belongs. */
- } s;
- struct cvmx_usbcx_grxstspd_s cn30xx;
- struct cvmx_usbcx_grxstspd_s cn31xx;
- struct cvmx_usbcx_grxstspd_s cn50xx;
- struct cvmx_usbcx_grxstspd_s cn52xx;
- struct cvmx_usbcx_grxstspd_s cn52xxp1;
- struct cvmx_usbcx_grxstspd_s cn56xx;
- struct cvmx_usbcx_grxstspd_s cn56xxp1;
-};
-typedef union cvmx_usbcx_grxstspd cvmx_usbcx_grxstspd_t;
-
-/**
* cvmx_usbc#_grxstsph
*
* Receive Status Read and Pop Register, Host Mode (GRXSTSPH)
@@ -2154,125 +783,6 @@ union cvmx_usbcx_grxstsph
typedef union cvmx_usbcx_grxstsph cvmx_usbcx_grxstsph_t;
/**
- * cvmx_usbc#_grxstsrd
- *
- * Receive Status Debug Read Register, Device Mode (GRXSTSRD)
- *
- * A read to the Receive Status Debug Read register returns the contents of the top of the Receive FIFO.
- * This Description is only valid when the core is in Device Mode. For Host Mode use USBC_GRXSTSRH instead.
- * NOTE: GRXSTSRH and GRXSTSRD are physically the same register and share the same offset in the O2P USB core.
- * The offset difference shown in this document is for software clarity and is actually ignored by the
- * hardware.
- */
-union cvmx_usbcx_grxstsrd
-{
- uint32_t u32;
- struct cvmx_usbcx_grxstsrd_s
- {
- uint32_t reserved_25_31 : 7;
- uint32_t fn : 4; /**< Frame Number (FN)
- This is the least significant 4 bits of the (micro)frame number in
- which the packet is received on the USB. This field is supported
- only when the isochronous OUT endpoints are supported. */
- uint32_t pktsts : 4; /**< Packet Status (PktSts)
- Indicates the status of the received packet
- * 4'b0001: Glogal OUT NAK (triggers an interrupt)
- * 4'b0010: OUT data packet received
- * 4'b0100: SETUP transaction completed (triggers an interrupt)
- * 4'b0110: SETUP data packet received
- * Others: Reserved */
- uint32_t dpid : 2; /**< Data PID (DPID)
- * 2'b00: DATA0
- * 2'b10: DATA1
- * 2'b01: DATA2
- * 2'b11: MDATA */
- uint32_t bcnt : 11; /**< Byte Count (BCnt)
- Indicates the byte count of the received data packet */
- uint32_t epnum : 4; /**< Endpoint Number (EPNum)
- Indicates the endpoint number to which the current received
- packet belongs. */
- } s;
- struct cvmx_usbcx_grxstsrd_s cn30xx;
- struct cvmx_usbcx_grxstsrd_s cn31xx;
- struct cvmx_usbcx_grxstsrd_s cn50xx;
- struct cvmx_usbcx_grxstsrd_s cn52xx;
- struct cvmx_usbcx_grxstsrd_s cn52xxp1;
- struct cvmx_usbcx_grxstsrd_s cn56xx;
- struct cvmx_usbcx_grxstsrd_s cn56xxp1;
-};
-typedef union cvmx_usbcx_grxstsrd cvmx_usbcx_grxstsrd_t;
-
-/**
- * cvmx_usbc#_grxstsrh
- *
- * Receive Status Debug Read Register, Host Mode (GRXSTSRH)
- *
- * A read to the Receive Status Debug Read register returns the contents of the top of the Receive FIFO.
- * This Description is only valid when the core is in Host Mode. For Device Mode use USBC_GRXSTSRD instead.
- * NOTE: GRXSTSRH and GRXSTSRD are physically the same register and share the same offset in the O2P USB core.
- * The offset difference shown in this document is for software clarity and is actually ignored by the
- * hardware.
- */
-union cvmx_usbcx_grxstsrh
-{
- uint32_t u32;
- struct cvmx_usbcx_grxstsrh_s
- {
- uint32_t reserved_21_31 : 11;
- uint32_t pktsts : 4; /**< Packet Status (PktSts)
- Indicates the status of the received packet
- * 4'b0010: IN data packet received
- * 4'b0011: IN transfer completed (triggers an interrupt)
- * 4'b0101: Data toggle error (triggers an interrupt)
- * 4'b0111: Channel halted (triggers an interrupt)
- * Others: Reserved */
- uint32_t dpid : 2; /**< Data PID (DPID)
- * 2'b00: DATA0
- * 2'b10: DATA1
- * 2'b01: DATA2
- * 2'b11: MDATA */
- uint32_t bcnt : 11; /**< Byte Count (BCnt)
- Indicates the byte count of the received IN data packet */
- uint32_t chnum : 4; /**< Channel Number (ChNum)
- Indicates the channel number to which the current received
- packet belongs. */
- } s;
- struct cvmx_usbcx_grxstsrh_s cn30xx;
- struct cvmx_usbcx_grxstsrh_s cn31xx;
- struct cvmx_usbcx_grxstsrh_s cn50xx;
- struct cvmx_usbcx_grxstsrh_s cn52xx;
- struct cvmx_usbcx_grxstsrh_s cn52xxp1;
- struct cvmx_usbcx_grxstsrh_s cn56xx;
- struct cvmx_usbcx_grxstsrh_s cn56xxp1;
-};
-typedef union cvmx_usbcx_grxstsrh cvmx_usbcx_grxstsrh_t;
-
-/**
- * cvmx_usbc#_gsnpsid
- *
- * Synopsys ID Register (GSNPSID)
- *
- * This is a read-only register that contains the release number of the core being used.
- */
-union cvmx_usbcx_gsnpsid
-{
- uint32_t u32;
- struct cvmx_usbcx_gsnpsid_s
- {
- uint32_t synopsysid : 32; /**< 0x4F54\<version\>A, release number of the core being used.
- 0x4F54220A => pass1.x, 0x4F54240A => pass2.x */
- } s;
- struct cvmx_usbcx_gsnpsid_s cn30xx;
- struct cvmx_usbcx_gsnpsid_s cn31xx;
- struct cvmx_usbcx_gsnpsid_s cn50xx;
- struct cvmx_usbcx_gsnpsid_s cn52xx;
- struct cvmx_usbcx_gsnpsid_s cn52xxp1;
- struct cvmx_usbcx_gsnpsid_s cn56xx;
- struct cvmx_usbcx_gsnpsid_s cn56xxp1;
-};
-typedef union cvmx_usbcx_gsnpsid cvmx_usbcx_gsnpsid_t;
-
-/**
* cvmx_usbc#_gusbcfg
*
* Core USB Configuration Register (GUSBCFG)
@@ -3005,82 +1515,4 @@ union cvmx_usbcx_hptxsts
};
typedef union cvmx_usbcx_hptxsts cvmx_usbcx_hptxsts_t;
-/**
- * cvmx_usbc#_nptxdfifo#
- *
- * NPTX Data Fifo (NPTXDFIFO)
- *
- * A slave mode application uses this register to access the Tx FIFO for channel n.
- */
-union cvmx_usbcx_nptxdfifox
-{
- uint32_t u32;
- struct cvmx_usbcx_nptxdfifox_s
- {
- uint32_t data : 32; /**< Reserved */
- } s;
- struct cvmx_usbcx_nptxdfifox_s cn30xx;
- struct cvmx_usbcx_nptxdfifox_s cn31xx;
- struct cvmx_usbcx_nptxdfifox_s cn50xx;
- struct cvmx_usbcx_nptxdfifox_s cn52xx;
- struct cvmx_usbcx_nptxdfifox_s cn52xxp1;
- struct cvmx_usbcx_nptxdfifox_s cn56xx;
- struct cvmx_usbcx_nptxdfifox_s cn56xxp1;
-};
-typedef union cvmx_usbcx_nptxdfifox cvmx_usbcx_nptxdfifox_t;
-
-/**
- * cvmx_usbc#_pcgcctl
- *
- * Power and Clock Gating Control Register (PCGCCTL)
- *
- * The application can use this register to control the core's power-down and clock gating features.
- */
-union cvmx_usbcx_pcgcctl
-{
- uint32_t u32;
- struct cvmx_usbcx_pcgcctl_s
- {
- uint32_t reserved_5_31 : 27;
- uint32_t physuspended : 1; /**< PHY Suspended. (PhySuspended)
- Indicates that the PHY has been suspended. After the
- application sets the Stop Pclk bit (bit 0), this bit is updated once
- the PHY is suspended.
- Since the UTMI+ PHY suspend is controlled through a port, the
- UTMI+ PHY is suspended immediately after Stop Pclk is set.
- However, the ULPI PHY takes a few clocks to suspend,
- because the suspend information is conveyed through the ULPI
- protocol to the ULPI PHY. */
- uint32_t rstpdwnmodule : 1; /**< Reset Power-Down Modules (RstPdwnModule)
- This bit is valid only in Partial Power-Down mode. The
- application sets this bit when the power is turned off. The
- application clears this bit after the power is turned on and the
- PHY clock is up. */
- uint32_t pwrclmp : 1; /**< Power Clamp (PwrClmp)
- This bit is only valid in Partial Power-Down mode. The
- application sets this bit before the power is turned off to clamp
- the signals between the power-on modules and the power-off
- modules. The application clears the bit to disable the clamping
- before the power is turned on. */
- uint32_t gatehclk : 1; /**< Gate Hclk (GateHclk)
- The application sets this bit to gate hclk to modules other than
- the AHB Slave and Master and wakeup logic when the USB is
- suspended or the session is not valid. The application clears
- this bit when the USB is resumed or a new session starts. */
- uint32_t stoppclk : 1; /**< Stop Pclk (StopPclk)
- The application sets this bit to stop the PHY clock (phy_clk)
- when the USB is suspended, the session is not valid, or the
- device is disconnected. The application clears this bit when the
- USB is resumed or a new session starts. */
- } s;
- struct cvmx_usbcx_pcgcctl_s cn30xx;
- struct cvmx_usbcx_pcgcctl_s cn31xx;
- struct cvmx_usbcx_pcgcctl_s cn50xx;
- struct cvmx_usbcx_pcgcctl_s cn52xx;
- struct cvmx_usbcx_pcgcctl_s cn52xxp1;
- struct cvmx_usbcx_pcgcctl_s cn56xx;
- struct cvmx_usbcx_pcgcctl_s cn56xxp1;
-};
-typedef union cvmx_usbcx_pcgcctl cvmx_usbcx_pcgcctl_t;
-
#endif

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