path: root/Documentation/devicetree/bindings/bus
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authorFlorian Fainelli <f.fainelli@gmail.com>2014-05-19 20:06:00 (GMT)
committerArnd Bergmann <arnd@arndb.de>2014-05-23 22:58:43 (GMT)
commite53c07724809bd3e103174fd27c5b6f00582a252 (patch)
treee1d012ffc76fe86ab8cba667c43d2e5c2e79f5dc /Documentation/devicetree/bindings/bus
parent44127b771d9c31dcb5ab90d9093a4d48877738bc (diff)
Documentation: devicetree: add Broadcom GISB arbiter bindings
This patch adds the Broadcom GISB arbiter Device Tree binding that is used on all Broadcom Set-top-box System-on-a-chip. Signed-off-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Diffstat (limited to 'Documentation/devicetree/bindings/bus')
1 files changed, 30 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/bus/brcm,gisb-arb.txt b/Documentation/devicetree/bindings/bus/brcm,gisb-arb.txt
new file mode 100644
index 0000000..e2d501d
--- /dev/null
+++ b/Documentation/devicetree/bindings/bus/brcm,gisb-arb.txt
@@ -0,0 +1,30 @@
+Broadcom GISB bus Arbiter controller
+Required properties:
+- compatible: should be "brcm,gisb-arb"
+- reg: specifies the base physical address and size of the registers
+- interrupt-parent: specifies the phandle to the parent interrupt controller
+ this arbiter gets interrupt line from
+- interrupts: specifies the two interrupts (timeout and TEA) to be used from
+ the parent interrupt controller
+Optional properties:
+- brcm,gisb-arb-master-mask: 32-bits wide bitmask used to specify which GISB
+ masters are valid at the system level
+- brcm,gisb-arb-master-names: string list of the litteral name of the GISB
+ masters. Should match the number of bits set in brcm,gisb-master-mask and
+ the order in which they appear
+gisb-arb@f0400000 {
+ compatible = "brcm,gisb-arb";
+ reg = <0xf0400000 0x800>;
+ interrupts = <0>, <2>;
+ interrupt-parent = <&sun_l2_intc>;
+ brcm,gisb-arb-master-mask = <0x7>;
+ brcm,gisb-arb-master-names = "bsp_0", "scpu_0", "cpu_0";

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