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authorUlrich Hecht <ulrich.hecht+renesas@gmail.com>2014-09-02 11:13:04 +0200
committerSimon Horman <horms+renesas@verge.net.au>2014-09-10 09:08:10 +0900
commitb32c44b93af31e9163514df0f3ac2791972eb124 (patch)
tree58807bc6f0e2f103a8b63cb589d882e267c325bf /Documentation/devicetree/bindings/clock
parent8de078f189da45453d2ed2a04288e329cc169731 (diff)
clk: shmobile: Add r8a7740, sh73a0 SoCs to MSTP bindings
Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Diffstat (limited to 'Documentation/devicetree/bindings/clock')
-rw-r--r--Documentation/devicetree/bindings/clock/renesas,cpg-mstp-clocks.txt2
1 files changed, 2 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/clock/renesas,cpg-mstp-clocks.txt b/Documentation/devicetree/bindings/clock/renesas,cpg-mstp-clocks.txt
index 8a92b5fb3540..8f1424f0fa43 100644
--- a/Documentation/devicetree/bindings/clock/renesas,cpg-mstp-clocks.txt
+++ b/Documentation/devicetree/bindings/clock/renesas,cpg-mstp-clocks.txt
@@ -11,9 +11,11 @@ Required Properties:
- compatible: Must be one of the following
- "renesas,r7s72100-mstp-clocks" for R7S72100 (RZ) MSTP gate clocks
+ - "renesas,r8a7740-mstp-clocks" for R8A7740 (R-Mobile A1) MSTP gate clocks
- "renesas,r8a7779-mstp-clocks" for R8A7779 (R-Car H1) MSTP gate clocks
- "renesas,r8a7790-mstp-clocks" for R8A7790 (R-Car H2) MSTP gate clocks
- "renesas,r8a7791-mstp-clocks" for R8A7791 (R-Car M2) MSTP gate clocks
+ - "renesas,sh73a0-mstp-clocks" for SH73A0 (SH-MobileAG5) MSTP gate clocks
- "renesas,cpg-mstp-clock" for generic MSTP gate clocks
- reg: Base address and length of the I/O mapped registers used by the MSTP
clocks. The first register is the clock control register and is mandatory.

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