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authorLinus Torvalds <torvalds@linux-foundation.org>2014-08-08 11:14:29 -0700
committerLinus Torvalds <torvalds@linux-foundation.org>2014-08-08 11:14:29 -0700
commitb3345d7c57d70e6cb6749af25cdbe80515582e99 (patch)
tree04cce706bc7e944ad1fb257108a8ae735948f97f /Documentation/devicetree/bindings/clock
parent44c916d58b9ef1f2c4aec2def57fa8289c716a60 (diff)
parentc2fff85e21818952aa0ee5778926beee6c03e579 (diff)
Merge tag 'soc-for-3.17' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM SoC platform changes from Olof Johansson: "This is the bulk of new SoC enablement and other platform changes for 3.17: - Samsung S5PV210 has been converted to DT and multiplatform - Clock drivers and bindings for some of the lower-end i.MX 1/2 platforms - Kirkwood, one of the popular Marvell platforms, is folded into the mvebu platform code, removing mach-kirkwood - Hwmod data for TI AM43xx and DRA7 platforms - More additions of Renesas shmobile platform support - Removal of plat-samsung contents that can be removed with S5PV210 being multiplatform/DT-enabled and the other two old platforms being removed New platforms (most with only basic support right now): - Hisilicon X5HD2 settop box chipset is introduced - Mediatek MT6589 (mobile chipset) is introduced - Broadcom BCM7xxx settop box chipset is introduced + as usual a lot other pieces all over the platform code" * tag 'soc-for-3.17' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (240 commits) ARM: hisi: remove smp from machine descriptor power: reset: move hisilicon reboot code ARM: dts: Add hix5hd2-dkb dts file. ARM: debug: Rename Hi3716 to HIX5HD2 ARM: hisi: enable hix5hd2 SoC ARM: hisi: add ARCH_HISI MAINTAINERS: add entry for Broadcom ARM STB architecture ARM: brcmstb: select GISB arbiter and interrupt drivers ARM: brcmstb: add infrastructure for ARM-based Broadcom STB SoCs ARM: configs: enable SMP in bcm_defconfig ARM: add SMP support for Broadcom mobile SoCs Documentation: arm: misc updates to Marvell EBU SoC status Documentation: arm: add URLs to public datasheets for the Marvell Armada XP SoC ARM: mvebu: fix build without platforms selected ARM: mvebu: add cpuidle support for Armada 38x ARM: mvebu: add cpuidle support for Armada 370 cpuidle: mvebu: add Armada 38x support cpuidle: mvebu: add Armada 370 support cpuidle: mvebu: rename the driver from armada-370-xp to mvebu-v7 ARM: mvebu: export the SCU address ...
Diffstat (limited to 'Documentation/devicetree/bindings/clock')
-rw-r--r--Documentation/devicetree/bindings/clock/arm-integrator.txt4
-rw-r--r--Documentation/devicetree/bindings/clock/clk-s5pv210-audss.txt53
-rw-r--r--Documentation/devicetree/bindings/clock/imx1-clock.txt26
-rw-r--r--Documentation/devicetree/bindings/clock/imx21-clock.txt28
-rw-r--r--Documentation/devicetree/bindings/clock/imx27-clock.txt127
-rw-r--r--Documentation/devicetree/bindings/clock/imx6q-clock.txt220
-rw-r--r--Documentation/devicetree/bindings/clock/mvebu-cpu-clock.txt5
-rw-r--r--Documentation/devicetree/bindings/clock/samsung,s5pv210-clock.txt78
8 files changed, 211 insertions, 330 deletions
diff --git a/Documentation/devicetree/bindings/clock/arm-integrator.txt b/Documentation/devicetree/bindings/clock/arm-integrator.txt
index 652914b17b95..ecc69520bcea 100644
--- a/Documentation/devicetree/bindings/clock/arm-integrator.txt
+++ b/Documentation/devicetree/bindings/clock/arm-integrator.txt
@@ -1,4 +1,4 @@
-Clock bindings for ARM Integrator Core Module clocks
+Clock bindings for ARM Integrator and Versatile Core Module clocks
Auxilary Oscillator Clock
@@ -12,7 +12,7 @@ parent node.
Required properties:
-- compatible: must be "arm,integrator-cm-auxosc"
+- compatible: must be "arm,integrator-cm-auxosc" or "arm,versatile-cm-auxosc"
- #clock-cells: must be <0>
Optional properties:
diff --git a/Documentation/devicetree/bindings/clock/clk-s5pv210-audss.txt b/Documentation/devicetree/bindings/clock/clk-s5pv210-audss.txt
new file mode 100644
index 000000000000..4fc869b69d4a
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/clk-s5pv210-audss.txt
@@ -0,0 +1,53 @@
+* Samsung Audio Subsystem Clock Controller
+
+The Samsung Audio Subsystem clock controller generates and supplies clocks
+to Audio Subsystem block available in the S5PV210 and compatible SoCs.
+
+Required Properties:
+
+- compatible: should be "samsung,s5pv210-audss-clock".
+- reg: physical base address and length of the controller's register set.
+
+- #clock-cells: should be 1.
+
+- clocks:
+ - hclk: AHB bus clock of the Audio Subsystem.
+ - xxti: Optional fixed rate PLL reference clock, parent of mout_audss. If
+ not specified (i.e. xusbxti is used for PLL reference), it is fixed to
+ a clock named "xxti".
+ - fout_epll: Input PLL to the AudioSS block, parent of mout_audss.
+ - iiscdclk0: Optional external i2s clock, parent of mout_i2s. If not
+ specified, it is fixed to a clock named "iiscdclk0".
+ - sclk_audio0: Audio bus clock, parent of mout_i2s.
+
+- clock-names: Aliases for the above clocks. They should be "hclk",
+ "xxti", "fout_epll", "iiscdclk0", and "sclk_audio0" respectively.
+
+All available clocks are defined as preprocessor macros in
+dt-bindings/clock/s5pv210-audss-clk.h header and can be used in device
+tree sources.
+
+Example: Clock controller node.
+
+ clk_audss: clock-controller@c0900000 {
+ compatible = "samsung,s5pv210-audss-clock";
+ reg = <0xc0900000 0x1000>;
+ #clock-cells = <1>;
+ clock-names = "hclk", "xxti",
+ "fout_epll", "sclk_audio0";
+ clocks = <&clocks DOUT_HCLKP>, <&xxti>,
+ <&clocks FOUT_EPLL>, <&clocks SCLK_AUDIO0>;
+ };
+
+Example: I2S controller node that consumes the clock generated by the clock
+ controller. Refer to the standard clock bindings for information
+ about 'clocks' and 'clock-names' property.
+
+ i2s0: i2s@03830000 {
+ /* ... */
+ clock-names = "iis", "i2s_opclk0",
+ "i2s_opclk1";
+ clocks = <&clk_audss CLK_I2S>, <&clk_audss CLK_I2S>,
+ <&clk_audss CLK_DOUT_AUD_BUS>;
+ /* ... */
+ };
diff --git a/Documentation/devicetree/bindings/clock/imx1-clock.txt b/Documentation/devicetree/bindings/clock/imx1-clock.txt
new file mode 100644
index 000000000000..b7adf4e3ea98
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/imx1-clock.txt
@@ -0,0 +1,26 @@
+* Clock bindings for Freescale i.MX1 CPUs
+
+Required properties:
+- compatible: Should be "fsl,imx1-ccm".
+- reg: Address and length of the register set.
+- #clock-cells: Should be <1>.
+
+The clock consumer should specify the desired clock by having the clock
+ID in its "clocks" phandle cell. See include/dt-bindings/clock/imx1-clock.h
+for the full list of i.MX1 clock IDs.
+
+Examples:
+ clks: ccm@0021b000 {
+ #clock-cells = <1>;
+ compatible = "fsl,imx1-ccm";
+ reg = <0x0021b000 0x1000>;
+ };
+
+ pwm: pwm@00208000 {
+ #pwm-cells = <2>;
+ compatible = "fsl,imx1-pwm";
+ reg = <0x00208000 0x1000>;
+ interrupts = <34>;
+ clocks = <&clks IMX1_CLK_DUMMY>, <&clks IMX1_CLK_PER1>;
+ clock-names = "ipg", "per";
+ };
diff --git a/Documentation/devicetree/bindings/clock/imx21-clock.txt b/Documentation/devicetree/bindings/clock/imx21-clock.txt
new file mode 100644
index 000000000000..c3b0db437c48
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/imx21-clock.txt
@@ -0,0 +1,28 @@
+* Clock bindings for Freescale i.MX21
+
+Required properties:
+- compatible : Should be "fsl,imx21-ccm".
+- reg : Address and length of the register set.
+- interrupts : Should contain CCM interrupt.
+- #clock-cells: Should be <1>.
+
+The clock consumer should specify the desired clock by having the clock
+ID in its "clocks" phandle cell. See include/dt-bindings/clock/imx21-clock.h
+for the full list of i.MX21 clock IDs.
+
+Examples:
+ clks: ccm@10027000{
+ compatible = "fsl,imx21-ccm";
+ reg = <0x10027000 0x800>;
+ #clock-cells = <1>;
+ };
+
+ uart1: serial@1000a000 {
+ compatible = "fsl,imx21-uart";
+ reg = <0x1000a000 0x1000>;
+ interrupts = <20>;
+ clocks = <&clks IMX21_CLK_UART1_IPG_GATE>,
+ <&clks IMX21_CLK_PER1>;
+ clock-names = "ipg", "per";
+ status = "disabled";
+ };
diff --git a/Documentation/devicetree/bindings/clock/imx27-clock.txt b/Documentation/devicetree/bindings/clock/imx27-clock.txt
index 6bc9fd2c6631..cc05de9ec393 100644
--- a/Documentation/devicetree/bindings/clock/imx27-clock.txt
+++ b/Documentation/devicetree/bindings/clock/imx27-clock.txt
@@ -7,117 +7,22 @@ Required properties:
- #clock-cells: Should be <1>
The clock consumer should specify the desired clock by having the clock
-ID in its "clocks" phandle cell. The following is a full list of i.MX27
-clocks and IDs.
-
- Clock ID
- -----------------------
- dummy 0
- ckih 1
- ckil 2
- mpll 3
- spll 4
- mpll_main2 5
- ahb 6
- ipg 7
- nfc_div 8
- per1_div 9
- per2_div 10
- per3_div 11
- per4_div 12
- vpu_sel 13
- vpu_div 14
- usb_div 15
- cpu_sel 16
- clko_sel 17
- cpu_div 18
- clko_div 19
- ssi1_sel 20
- ssi2_sel 21
- ssi1_div 22
- ssi2_div 23
- clko_en 24
- ssi2_ipg_gate 25
- ssi1_ipg_gate 26
- slcdc_ipg_gate 27
- sdhc3_ipg_gate 28
- sdhc2_ipg_gate 29
- sdhc1_ipg_gate 30
- scc_ipg_gate 31
- sahara_ipg_gate 32
- rtc_ipg_gate 33
- pwm_ipg_gate 34
- owire_ipg_gate 35
- lcdc_ipg_gate 36
- kpp_ipg_gate 37
- iim_ipg_gate 38
- i2c2_ipg_gate 39
- i2c1_ipg_gate 40
- gpt6_ipg_gate 41
- gpt5_ipg_gate 42
- gpt4_ipg_gate 43
- gpt3_ipg_gate 44
- gpt2_ipg_gate 45
- gpt1_ipg_gate 46
- gpio_ipg_gate 47
- fec_ipg_gate 48
- emma_ipg_gate 49
- dma_ipg_gate 50
- cspi3_ipg_gate 51
- cspi2_ipg_gate 52
- cspi1_ipg_gate 53
- nfc_baud_gate 54
- ssi2_baud_gate 55
- ssi1_baud_gate 56
- vpu_baud_gate 57
- per4_gate 58
- per3_gate 59
- per2_gate 60
- per1_gate 61
- usb_ahb_gate 62
- slcdc_ahb_gate 63
- sahara_ahb_gate 64
- lcdc_ahb_gate 65
- vpu_ahb_gate 66
- fec_ahb_gate 67
- emma_ahb_gate 68
- emi_ahb_gate 69
- dma_ahb_gate 70
- csi_ahb_gate 71
- brom_ahb_gate 72
- ata_ahb_gate 73
- wdog_ipg_gate 74
- usb_ipg_gate 75
- uart6_ipg_gate 76
- uart5_ipg_gate 77
- uart4_ipg_gate 78
- uart3_ipg_gate 79
- uart2_ipg_gate 80
- uart1_ipg_gate 81
- ckih_div1p5 82
- fpm 83
- mpll_osc_sel 84
- mpll_sel 85
- spll_gate 86
- mshc_div 87
- rtic_ipg_gate 88
- mshc_ipg_gate 89
- rtic_ahb_gate 90
- mshc_baud_gate 91
+ID in its "clocks" phandle cell. See include/dt-bindings/clock/imx27-clock.h
+for the full list of i.MX27 clock IDs.
Examples:
+ clks: ccm@10027000{
+ compatible = "fsl,imx27-ccm";
+ reg = <0x10027000 0x1000>;
+ #clock-cells = <1>;
+ };
-clks: ccm@10027000{
- compatible = "fsl,imx27-ccm";
- reg = <0x10027000 0x1000>;
- #clock-cells = <1>;
-};
-
-uart1: serial@1000a000 {
- compatible = "fsl,imx27-uart", "fsl,imx21-uart";
- reg = <0x1000a000 0x1000>;
- interrupts = <20>;
- clocks = <&clks 81>, <&clks 61>;
- clock-names = "ipg", "per";
- status = "disabled";
-};
+ uart1: serial@1000a000 {
+ compatible = "fsl,imx27-uart", "fsl,imx21-uart";
+ reg = <0x1000a000 0x1000>;
+ interrupts = <20>;
+ clocks = <&clks IMX27_CLK_UART1_IPG_GATE>,
+ <&clks IMX27_CLK_PER1_GATE>;
+ clock-names = "ipg", "per";
+ status = "disabled";
+ };
diff --git a/Documentation/devicetree/bindings/clock/imx6q-clock.txt b/Documentation/devicetree/bindings/clock/imx6q-clock.txt
index 90ec91fe5ce0..9252912a5b0e 100644
--- a/Documentation/devicetree/bindings/clock/imx6q-clock.txt
+++ b/Documentation/devicetree/bindings/clock/imx6q-clock.txt
@@ -7,223 +7,13 @@ Required properties:
- #clock-cells: Should be <1>
The clock consumer should specify the desired clock by having the clock
-ID in its "clocks" phandle cell. The following is a full list of i.MX6Q
-clocks and IDs.
-
- Clock ID
- ---------------------------
- dummy 0
- ckil 1
- ckih 2
- osc 3
- pll2_pfd0_352m 4
- pll2_pfd1_594m 5
- pll2_pfd2_396m 6
- pll3_pfd0_720m 7
- pll3_pfd1_540m 8
- pll3_pfd2_508m 9
- pll3_pfd3_454m 10
- pll2_198m 11
- pll3_120m 12
- pll3_80m 13
- pll3_60m 14
- twd 15
- step 16
- pll1_sw 17
- periph_pre 18
- periph2_pre 19
- periph_clk2_sel 20
- periph2_clk2_sel 21
- axi_sel 22
- esai_sel 23
- asrc_sel 24
- spdif_sel 25
- gpu2d_axi 26
- gpu3d_axi 27
- gpu2d_core_sel 28
- gpu3d_core_sel 29
- gpu3d_shader_sel 30
- ipu1_sel 31
- ipu2_sel 32
- ldb_di0_sel 33
- ldb_di1_sel 34
- ipu1_di0_pre_sel 35
- ipu1_di1_pre_sel 36
- ipu2_di0_pre_sel 37
- ipu2_di1_pre_sel 38
- ipu1_di0_sel 39
- ipu1_di1_sel 40
- ipu2_di0_sel 41
- ipu2_di1_sel 42
- hsi_tx_sel 43
- pcie_axi_sel 44
- ssi1_sel 45
- ssi2_sel 46
- ssi3_sel 47
- usdhc1_sel 48
- usdhc2_sel 49
- usdhc3_sel 50
- usdhc4_sel 51
- enfc_sel 52
- emi_sel 53
- emi_slow_sel 54
- vdo_axi_sel 55
- vpu_axi_sel 56
- cko1_sel 57
- periph 58
- periph2 59
- periph_clk2 60
- periph2_clk2 61
- ipg 62
- ipg_per 63
- esai_pred 64
- esai_podf 65
- asrc_pred 66
- asrc_podf 67
- spdif_pred 68
- spdif_podf 69
- can_root 70
- ecspi_root 71
- gpu2d_core_podf 72
- gpu3d_core_podf 73
- gpu3d_shader 74
- ipu1_podf 75
- ipu2_podf 76
- ldb_di0_podf 77
- ldb_di1_podf 78
- ipu1_di0_pre 79
- ipu1_di1_pre 80
- ipu2_di0_pre 81
- ipu2_di1_pre 82
- hsi_tx_podf 83
- ssi1_pred 84
- ssi1_podf 85
- ssi2_pred 86
- ssi2_podf 87
- ssi3_pred 88
- ssi3_podf 89
- uart_serial_podf 90
- usdhc1_podf 91
- usdhc2_podf 92
- usdhc3_podf 93
- usdhc4_podf 94
- enfc_pred 95
- enfc_podf 96
- emi_podf 97
- emi_slow_podf 98
- vpu_axi_podf 99
- cko1_podf 100
- axi 101
- mmdc_ch0_axi_podf 102
- mmdc_ch1_axi_podf 103
- arm 104
- ahb 105
- apbh_dma 106
- asrc 107
- can1_ipg 108
- can1_serial 109
- can2_ipg 110
- can2_serial 111
- ecspi1 112
- ecspi2 113
- ecspi3 114
- ecspi4 115
- ecspi5 116
- enet 117
- esai 118
- gpt_ipg 119
- gpt_ipg_per 120
- gpu2d_core 121
- gpu3d_core 122
- hdmi_iahb 123
- hdmi_isfr 124
- i2c1 125
- i2c2 126
- i2c3 127
- iim 128
- enfc 129
- ipu1 130
- ipu1_di0 131
- ipu1_di1 132
- ipu2 133
- ipu2_di0 134
- ldb_di0 135
- ldb_di1 136
- ipu2_di1 137
- hsi_tx 138
- mlb 139
- mmdc_ch0_axi 140
- mmdc_ch1_axi 141
- ocram 142
- openvg_axi 143
- pcie_axi 144
- pwm1 145
- pwm2 146
- pwm3 147
- pwm4 148
- per1_bch 149
- gpmi_bch_apb 150
- gpmi_bch 151
- gpmi_io 152
- gpmi_apb 153
- sata 154
- sdma 155
- spba 156
- ssi1 157
- ssi2 158
- ssi3 159
- uart_ipg 160
- uart_serial 161
- usboh3 162
- usdhc1 163
- usdhc2 164
- usdhc3 165
- usdhc4 166
- vdo_axi 167
- vpu_axi 168
- cko1 169
- pll1_sys 170
- pll2_bus 171
- pll3_usb_otg 172
- pll4_audio 173
- pll5_video 174
- pll8_mlb 175
- pll7_usb_host 176
- pll6_enet 177
- ssi1_ipg 178
- ssi2_ipg 179
- ssi3_ipg 180
- rom 181
- usbphy1 182
- usbphy2 183
- ldb_di0_div_3_5 184
- ldb_di1_div_3_5 185
- sata_ref 186
- sata_ref_100m 187
- pcie_ref 188
- pcie_ref_125m 189
- enet_ref 190
- usbphy1_gate 191
- usbphy2_gate 192
- pll4_post_div 193
- pll5_post_div 194
- pll5_video_div 195
- eim_slow 196
- spdif 197
- cko2_sel 198
- cko2_podf 199
- cko2 200
- cko 201
- vdoa 202
- pll4_audio_div 203
- lvds1_sel 204
- lvds2_sel 205
- lvds1_gate 206
- lvds2_gate 207
- esai_ahb 208
+ID in its "clocks" phandle cell. See include/dt-bindings/clock/imx6qdl-clock.h
+for the full list of i.MX6 Quad and DualLite clock IDs.
Examples:
+#include <dt-bindings/clock/imx6qdl-clock.h>
+
clks: ccm@020c4000 {
compatible = "fsl,imx6q-ccm";
reg = <0x020c4000 0x4000>;
@@ -235,7 +25,7 @@ uart1: serial@02020000 {
compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
reg = <0x02020000 0x4000>;
interrupts = <0 26 0x04>;
- clocks = <&clks 160>, <&clks 161>;
+ clocks = <&clks IMX6QDL_CLK_UART_IPG>, <&clks IMX6QDL_CLK_UART_SERIAL>;
clock-names = "ipg", "per";
status = "disabled";
};
diff --git a/Documentation/devicetree/bindings/clock/mvebu-cpu-clock.txt b/Documentation/devicetree/bindings/clock/mvebu-cpu-clock.txt
index feb830130714..99c214660bdc 100644
--- a/Documentation/devicetree/bindings/clock/mvebu-cpu-clock.txt
+++ b/Documentation/devicetree/bindings/clock/mvebu-cpu-clock.txt
@@ -3,14 +3,15 @@ Device Tree Clock bindings for cpu clock of Marvell EBU platforms
Required properties:
- compatible : shall be one of the following:
"marvell,armada-xp-cpu-clock" - cpu clocks for Armada XP
-- reg : Address and length of the clock complex register set
+- reg : Address and length of the clock complex register set, followed
+ by address and length of the PMU DFS registers
- #clock-cells : should be set to 1.
- clocks : shall be the input parent clock phandle for the clock.
cpuclk: clock-complex@d0018700 {
#clock-cells = <1>;
compatible = "marvell,armada-xp-cpu-clock";
- reg = <0xd0018700 0xA0>;
+ reg = <0xd0018700 0xA0>, <0x1c054 0x10>;
clocks = <&coreclk 1>;
}
diff --git a/Documentation/devicetree/bindings/clock/samsung,s5pv210-clock.txt b/Documentation/devicetree/bindings/clock/samsung,s5pv210-clock.txt
new file mode 100644
index 000000000000..effd9401c133
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/samsung,s5pv210-clock.txt
@@ -0,0 +1,78 @@
+* Samsung S5P6442/S5PC110/S5PV210 Clock Controller
+
+Samsung S5P6442, S5PC110 and S5PV210 SoCs contain integrated clock
+controller, which generates and supplies clock to various controllers
+within the SoC.
+
+Required Properties:
+
+- compatible: should be one of following:
+ - "samsung,s5pv210-clock" : for clock controller of Samsung
+ S5PC110/S5PV210 SoCs,
+ - "samsung,s5p6442-clock" : for clock controller of Samsung
+ S5P6442 SoC.
+
+- reg: physical base address of the controller and length of memory mapped
+ region.
+
+- #clock-cells: should be 1.
+
+All available clocks are defined as preprocessor macros in
+dt-bindings/clock/s5pv210.h header and can be used in device tree sources.
+
+External clocks:
+
+There are several clocks that are generated outside the SoC. It is expected
+that they are defined using standard clock bindings with following
+clock-output-names:
+ - "xxti": external crystal oscillator connected to XXTI and XXTO pins of
+the SoC,
+ - "xusbxti": external crystal oscillator connected to XUSBXTI and XUSBXTO
+pins of the SoC,
+
+A subset of above clocks available on given board shall be specified in
+board device tree, including the system base clock, as selected by XOM[0]
+pin of the SoC. Refer to generic fixed rate clock bindings
+documentation[1] for more information how to specify these clocks.
+
+[1] Documentation/devicetree/bindings/clock/fixed-clock.txt
+
+Example: Clock controller node:
+
+ clock: clock-controller@7e00f000 {
+ compatible = "samsung,s5pv210-clock";
+ reg = <0x7e00f000 0x1000>;
+ #clock-cells = <1>;
+ };
+
+Example: Required external clocks:
+
+ xxti: clock-xxti {
+ compatible = "fixed-clock";
+ clock-output-names = "xxti";
+ clock-frequency = <24000000>;
+ #clock-cells = <0>;
+ };
+
+ xusbxti: clock-xusbxti {
+ compatible = "fixed-clock";
+ clock-output-names = "xusbxti";
+ clock-frequency = <24000000>;
+ #clock-cells = <0>;
+ };
+
+Example: UART controller node that consumes the clock generated by the clock
+ controller (refer to the standard clock bindings for information about
+ "clocks" and "clock-names" properties):
+
+ uart0: serial@e2900000 {
+ compatible = "samsung,s5pv210-uart";
+ reg = <0xe2900000 0x400>;
+ interrupt-parent = <&vic1>;
+ interrupts = <10>;
+ clock-names = "uart", "clk_uart_baud0",
+ "clk_uart_baud1";
+ clocks = <&clocks UART0>, <&clocks UART0>,
+ <&clocks SCLK_UART0>;
+ status = "disabled";
+ };

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