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authorFeng Kan <fkan@apm.com>2014-07-31 12:03:26 -0700
committerLinus Walleij <linus.walleij@linaro.org>2014-08-28 14:20:45 +0200
commit1b5bda21b05ef1b3c5462d4f066fda7c68240dda (patch)
tree8ace49e9cf714bed0cff39e0f13ed8b0eb33fe74 /Documentation/devicetree/bindings/gpio
parent29cbf4589fc0dabef4dfc95dd9589c366ad2ec46 (diff)
Documentation: gpio: Add APM X-Gene SoC GPIO controller DTS binding
Documentation for APM X-Gene SoC GPIO controller DTS binding. Signed-off-by: Feng Kan <fkan@apm.com> Reviewed-by: Alexandre Courbot <acourbot@nvidia.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Diffstat (limited to 'Documentation/devicetree/bindings/gpio')
-rw-r--r--Documentation/devicetree/bindings/gpio/gpio-xgene.txt22
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diff --git a/Documentation/devicetree/bindings/gpio/gpio-xgene.txt b/Documentation/devicetree/bindings/gpio/gpio-xgene.txt
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+++ b/Documentation/devicetree/bindings/gpio/gpio-xgene.txt
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+APM X-Gene SoC GPIO controller bindings
+
+This is a gpio controller that is part of the flash controller.
+This gpio controller controls a total of 48 gpios.
+
+Required properties:
+- compatible: "apm,xgene-gpio" for X-Gene GPIO controller
+- reg: Physical base address and size of the controller's registers
+- #gpio-cells: Should be two.
+ - first cell is the pin number
+ - second cell is used to specify the gpio polarity:
+ 0 = active high
+ 1 = active low
+- gpio-controller: Marks the device node as a GPIO controller.
+
+Example:
+ gpio0: gpio0@1701c000 {
+ compatible = "apm,xgene-gpio";
+ reg = <0x0 0x1701c000 0x0 0x40>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };

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