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authorRussell King <rmk+kernel@arm.linux.org.uk>2013-06-18 17:20:32 +0100
committerWim Van Sebroeck <wim@iguana.be>2013-07-11 22:18:30 +0200
commit6910ceb5cababfefffc4ddc58a085a71c0ab9f22 (patch)
treee80d0356a22f65ff39be283561d5e3ae8e073803 /Documentation/devicetree/bindings/gpio
parentfa142ff5b3f67fab01f3d02a501b041b4266afdd (diff)
Watchdog: fix clearing of the watchdog interrupt
The bits in BRIDGE_CAUSE are documented as RW0C - read, write 0 to clear. If we read the register, mask off the watchdog bit, and write it back, we're actually clearing every interrupt which wasn't pending at the time we read the register - and that is racy. Fix this to only write ~WATCHDOG_BIT to the register, which means we write as zero only the watchdog bit. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk> Acked-by: Jason Cooper <jason@lakedaemon.net> Tested-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: Wim Van Sebroeck <wim@iguana.be>
Diffstat (limited to 'Documentation/devicetree/bindings/gpio')
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