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authorUlf Hansson <ulf.hansson@linaro.org>2014-02-14 12:27:08 (GMT)
committerChris Ball <chris@printf.net>2014-02-22 18:51:10 (GMT)
commitc0baf8485928b2db8a9530672d522d758746a2b6 (patch)
treec0bf4982b52ffca8ae77f9a3590f666590438873 /Documentation/devicetree/bindings/mmc
parentb66bd0e4d00c89102851c1bc9a0f738a4ad9ca2d (diff)
mmc: core: Add DT bindings for eMMC high-speed DDR 1.8/1.2V
Provide the option to configure these speed modes per host, for those host driver's that can't distinguish this in runtime. Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> Acked-by: Jaehoon Chung <jh80.chung@samsung.com> Signed-off-by: Chris Ball <chris@printf.net>
Diffstat (limited to 'Documentation/devicetree/bindings/mmc')
-rw-r--r--Documentation/devicetree/bindings/mmc/mmc.txt2
1 files changed, 2 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/mmc/mmc.txt b/Documentation/devicetree/bindings/mmc/mmc.txt
index bd2ce67..519d952 100644
--- a/Documentation/devicetree/bindings/mmc/mmc.txt
+++ b/Documentation/devicetree/bindings/mmc/mmc.txt
@@ -34,6 +34,8 @@ Optional properties:
- cap-power-off-card: powering off the card is safe
- cap-sdio-irq: enable SDIO IRQ signalling on this interface
- full-pwr-cycle: full power cycle of the card is supported
+- mmc-highspeed-ddr-1_8v: eMMC high-speed DDR mode(1.8V I/O) is supported
+- mmc-highspeed-ddr-1_2v: eMMC high-speed DDR mode(1.2V I/O) is supported
*NOTE* on CD and WP polarity. To use common for all SD/MMC host controllers line
polarity properties, we have to fix the meaning of the "normal" and "inverted"

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