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authorJingchang Lu <jingchang.lu@freescale.com>2014-07-14 09:41:10 (GMT)
committerGreg Kroah-Hartman <gregkh@linuxfoundation.org>2014-07-18 01:15:38 (GMT)
commit876496b8cd01b02f7eb561c27aeaf908e4c3f86e (patch)
treede885dc04d017f646b2094973088f35db1cb600f /Documentation/devicetree/bindings/serial
parent730c4e782c039caf40b467c35f595c005e94220c (diff)
dt-binding: fsl-lpuart: use exact SoC revision to document binding
use exact SoC revision instead of wildcard describing to make the binding more clearer. Signed-off-by: Jingchang Lu <jingchang.lu@freescale.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Diffstat (limited to 'Documentation/devicetree/bindings/serial')
-rw-r--r--Documentation/devicetree/bindings/serial/fsl-lpuart.txt6
1 files changed, 5 insertions, 1 deletions
diff --git a/Documentation/devicetree/bindings/serial/fsl-lpuart.txt b/Documentation/devicetree/bindings/serial/fsl-lpuart.txt
index a1d1205..c95005e 100644
--- a/Documentation/devicetree/bindings/serial/fsl-lpuart.txt
+++ b/Documentation/devicetree/bindings/serial/fsl-lpuart.txt
@@ -1,7 +1,11 @@
* Freescale low power universal asynchronous receiver/transmitter (lpuart)
Required properties:
-- compatible : Should be "fsl,<soc>-lpuart"
+- compatible :
+ - "fsl,vf610-lpuart" for lpuart compatible with the one integrated
+ on Vybrid vf610 SoC with 8-bit register organization
+ - "fsl,ls1021a-lpuart" for lpuart compatible with the one integrated
+ on LS1021A SoC with 32-bit big-endian register organization
- reg : Address and length of the register set for the device
- interrupts : Should contain uart interrupt
- clocks : phandle + clock specifier pairs, one for each entry in clock-names

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