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authorDaniel Mack <zonque@gmail.com>2013-08-12 08:37:16 (GMT)
committerMark Brown <broonie@linaro.org>2013-08-14 18:54:23 (GMT)
commita6e56c28a178cef5f93d1e11698a23a5482175d9 (patch)
tree89c6fd87f13ac178257e314320103e7c5f31b38c /Documentation/devicetree/bindings/serial
parent970d8a7152aa884b9bab6a8db1ff148ee22df899 (diff)
ARM: pxa: ssp: add DT bindings
This patch contains an ugly hack for looking up the the DMA request number. The problem here is that the implementation as it stands will allocate the DMA channel from the user of the ssp port, and hence we cannot allocate a real channel here. Signed-off-by: Daniel Mack <zonque@gmail.com> Acked-by: Haojian Zhuang <haojian.zhuang@gmail.com> Signed-off-by: Mark Brown <broonie@linaro.org>
Diffstat (limited to 'Documentation/devicetree/bindings/serial')
-rw-r--r--Documentation/devicetree/bindings/serial/mrvl,pxa-ssp.txt65
1 files changed, 65 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/serial/mrvl,pxa-ssp.txt b/Documentation/devicetree/bindings/serial/mrvl,pxa-ssp.txt
new file mode 100644
index 0000000..669b814
--- /dev/null
+++ b/Documentation/devicetree/bindings/serial/mrvl,pxa-ssp.txt
@@ -0,0 +1,65 @@
+Device tree bindings for Marvell PXA SSP ports
+
+Required properties:
+
+ - compatible: Must be one of
+ mrvl,pxa25x-ssp
+ mvrl,pxa25x-nssp
+ mrvl,pxa27x-ssp
+ mrvl,pxa3xx-ssp
+ mvrl,pxa168-ssp
+ mrvl,pxa910-ssp
+ mrvl,ce4100-ssp
+ mrvl,lpss-ssp
+
+ - reg: The memory base
+ - dmas: Two dma phandles, one for rx, one for tx
+ - dma-names: Must be "rx", "tx"
+
+
+Example for PXA3xx:
+
+ ssp0: ssp@41000000 {
+ compatible = "mrvl,pxa3xx-ssp";
+ reg = <0x41000000 0x40>;
+ ssp-id = <1>;
+ interrupts = <24>;
+ clock-names = "pxa27x-ssp.0";
+ dmas = <&dma 13
+ &dma 14>;
+ dma-names = "rx", "tx";
+ };
+
+ ssp1: ssp@41700000 {
+ compatible = "mrvl,pxa3xx-ssp";
+ reg = <0x41700000 0x40>;
+ ssp-id = <2>;
+ interrupts = <16>;
+ clock-names = "pxa27x-ssp.1";
+ dmas = <&dma 15
+ &dma 16>;
+ dma-names = "rx", "tx";
+ };
+
+ ssp2: ssp@41900000 {
+ compatibl3 = "mrvl,pxa3xx-ssp";
+ reg = <0x41900000 0x40>;
+ ssp-id = <3>;
+ interrupts = <0>;
+ clock-names = "pxa27x-ssp.2";
+ dmas = <&dma 66
+ &dma 67>;
+ dma-names = "rx", "tx";
+ };
+
+ ssp3: ssp@41a00000 {
+ compatible = "mrvl,pxa3xx-ssp";
+ reg = <0x41a00000 0x40>;
+ ssp-id = <4>;
+ interrupts = <13>;
+ clock-names = "pxa27x-ssp.3";
+ dmas = <&dma 2
+ &dma 3>;
+ dma-names = "rx", "tx";
+ };
+

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