path: root/Documentation/devicetree/bindings/spi
diff options
authorChao Fu <B44548@freescale.com>2014-02-12 07:29:05 (GMT)
committerMark Brown <broonie@linaro.org>2014-02-16 01:15:23 (GMT)
commit1acbdeb92c87fc18eade0815dedc257fe45b88b7 (patch)
tree8e4b34fade904bbd4e01c94f90212d9ad6654eba /Documentation/devicetree/bindings/spi
parent38dbfb59d1175ef458d006556061adeaa8751b72 (diff)
spi/fsl-dspi: Convert to use regmap and add big-endian support
Freescale DSPI module will have two endianess in different platform, but ARM is little endian. So when DSPI in big endian, core in little endian, readl and writel can not adjust R/W register in this condition. This patch will remove general readl/writel, and import regmap mechanism. Data endian will be transfered in regmap APIs. Documents: dspi add bool "big-endian" in dts node if DSPI module work in big endian. Signed-off-by: Chao Fu <b44548@freescale.com> Reviewed-by: Xiubo Li <Li.Xiubo@freescale.com> Signed-off-by: Mark Brown <broonie@linaro.org>
Diffstat (limited to 'Documentation/devicetree/bindings/spi')
1 files changed, 2 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/spi/spi-fsl-dspi.txt b/Documentation/devicetree/bindings/spi/spi-fsl-dspi.txt
index a1fb303..5376de4 100644
--- a/Documentation/devicetree/bindings/spi/spi-fsl-dspi.txt
+++ b/Documentation/devicetree/bindings/spi/spi-fsl-dspi.txt
@@ -10,6 +10,7 @@ Required properties:
- pinctrl-names: must contain a "default" entry.
- spi-num-chipselects : the number of the chipselect signals.
- bus-num : the slave chip chipselect signal number.
+- big-endian : if DSPI modudle is big endian, the bool will be set in node.
dspi0@4002c000 {
@@ -24,6 +25,7 @@ dspi0@4002c000 {
bus-num = <0>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_dspi0_1>;
+ big-endian;
status = "okay";
sflash: at26df081a@0 {

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