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authorSteffen Trumtrar <s.trumtrar@pengutronix.de>2014-06-13 13:36:18 (GMT)
committerMark Brown <broonie@linaro.org>2014-07-03 18:44:04 (GMT)
commit22dae17e7a5e8b79e5e56d1557234dda9e1dd8e2 (patch)
tree1105b3b03858f01270e32766f2cff06c49d9f5d9 /Documentation/devicetree/bindings/spi
parent7171511eaec5bf23fb06078f59784a3a0626b38f (diff)
spi: dw-mmio: add devicetree support
Allow probing the dw-mmio from devicetree. Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de> Signed-off-by: Mark Brown <broonie@linaro.org>
Diffstat (limited to 'Documentation/devicetree/bindings/spi')
-rw-r--r--Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.txt28
1 files changed, 28 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.txt b/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.txt
new file mode 100644
index 0000000..bd99193
--- /dev/null
+++ b/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.txt
@@ -0,0 +1,28 @@
+Synopsys DesignWare AMBA 2.0 Synchronous Serial Interface.
+
+Required properties:
+- compatible : "snps,dw-apb-ssi"
+- reg : The register base for the controller.
+- interrupts : One interrupt, used by the controller.
+- #address-cells : <1>, as required by generic SPI binding.
+- #size-cells : <0>, also as required by generic SPI binding.
+
+Optional properties:
+- cs-gpios : Specifies the gpio pis to be used for chipselects.
+- num-cs : The number of chipselects. If omitted, this will default to 4.
+
+Child nodes as per the generic SPI binding.
+
+Example:
+
+ spi@fff00000 {
+ compatible = "snps,dw-apb-ssi";
+ reg = <0xfff00000 0x1000>;
+ interrupts = <0 154 4>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ num-cs = <2>;
+ cs-gpios = <&gpio0 13 0>,
+ <&gpio0 14 0>;
+ };
+

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