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authorMurali Karicheri <m-karicheri2@ti.com>2014-08-01 16:40:32 (GMT)
committerMark Brown <broonie@linaro.org>2014-08-01 18:20:52 (GMT)
commita88e34ea213e1bdbd9b2dfca1e1e5fa68b9649a0 (patch)
tree98c14456c50633d5ed50da96ef7c98cccc215823 /Documentation/devicetree/bindings/spi
parent7480e755c6e6e890200e8998597e8d0baa51fa8e (diff)
spi: davinci: add support to configure gpio cs through dt
Currently driver supports only configuration of GPIO CS through platform data. This patch enhances the driver to configure GPIO CS through DT. Also update the DT binding documentation to reflect the availability of cs-gpios. Signed-off-by: Murali Karicheri <m-karicheri2@ti.com> Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com> Signed-off-by: Mark Brown <broonie@linaro.org>
Diffstat (limited to 'Documentation/devicetree/bindings/spi')
-rw-r--r--Documentation/devicetree/bindings/spi/spi-davinci.txt9
1 files changed, 8 insertions, 1 deletions
diff --git a/Documentation/devicetree/bindings/spi/spi-davinci.txt b/Documentation/devicetree/bindings/spi/spi-davinci.txt
index 6d0ac8d..f80887b 100644
--- a/Documentation/devicetree/bindings/spi/spi-davinci.txt
+++ b/Documentation/devicetree/bindings/spi/spi-davinci.txt
@@ -8,7 +8,8 @@ Required properties:
- "ti,dm6441-spi" for SPI used similar to that on DM644x SoC family
- "ti,da830-spi" for SPI used similar to that on DA8xx SoC family
- reg: Offset and length of SPI controller register space
-- num-cs: Number of chip selects
+- num-cs: Number of chip selects. This includes internal as well as
+ GPIO chip selects.
- ti,davinci-spi-intr-line: interrupt line used to connect the SPI
IP to the interrupt controller within the SoC. Possible values
are 0 and 1. Manual says one of the two possible interrupt
@@ -17,6 +18,12 @@ Required properties:
- interrupts: interrupt number mapped to CPU.
- clocks: spi clk phandle
+Optional:
+- cs-gpios: gpio chip selects
+ For example to have 3 internal CS and 2 GPIO CS, user could define
+ cs-gpios = <0>, <0>, <0>, <&gpio1 30 0>, <&gpio1 31 0>;
+ where first three are internal CS and last two are GPIO CS.
+
Example of a NOR flash slave device (n25q032) connected to DaVinci
SPI controller device over the SPI bus.

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