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authorJamie Iles <jamie@jamieiles.com>2011-08-01 17:25:19 +0100
committerHerbert Xu <herbert@gondor.apana.org.au>2011-08-10 19:00:26 +0800
commit30343ef1de348cd21cd7d0cebde3c0175b730e0b (patch)
treef70c2ba846c1f664a7be2e1f2d9b39d4c83c6996 /Documentation/devicetree/bindings
parent4efae8c9363e28892eaaf2a6463f2f5f255e6fb0 (diff)
crypto: picoxcell - support for device tree matching
Allow the crypto engines to be matched from device tree bindings. Cc: devicetree-discuss@lists.ozlabs.org Cc: Herbert Xu <herbert@gondor.apana.org.au> Signed-off-by: Jamie Iles <jamie@jamieiles.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
Diffstat (limited to 'Documentation/devicetree/bindings')
-rw-r--r--Documentation/devicetree/bindings/crypto/picochip-spacc.txt23
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diff --git a/Documentation/devicetree/bindings/crypto/picochip-spacc.txt b/Documentation/devicetree/bindings/crypto/picochip-spacc.txt
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+++ b/Documentation/devicetree/bindings/crypto/picochip-spacc.txt
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+Picochip picoXcell SPAcc (Security Protocol Accelerator) bindings
+
+Picochip picoXcell devices contain crypto offload engines that may be used for
+IPSEC and femtocell layer 2 ciphering.
+
+Required properties:
+ - compatible : "picochip,spacc-ipsec" for the IPSEC offload engine
+ "picochip,spacc-l2" for the femtocell layer 2 ciphering engine.
+ - reg : Offset and length of the register set for this device
+ - interrupt-parent : The interrupt controller that controls the SPAcc
+ interrupt.
+ - interrupts : The interrupt line from the SPAcc.
+ - ref-clock : The input clock that drives the SPAcc.
+
+Example SPAcc node:
+
+spacc@10000 {
+ compatible = "picochip,spacc-ipsec";
+ reg = <0x100000 0x10000>;
+ interrupt-parent = <&vic0>;
+ interrupts = <24>;
+ ref-clock = <&ipsec_clk>, "ref";
+};

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