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authorLennert Buytenhek <buytenh@wantstofly.org>2009-04-29 11:58:18 +0000
committerDavid S. Miller <davem@davemloft.net>2009-04-29 17:24:19 -0700
commit93af7aca44f0e82e67bda10a0fb73d383edcc8bd (patch)
treee5d336ee7b7eac1b2e0091e948085de284ae344c /Documentation/isdn
parent1319ebadf185933e6b7ff95211d3cef9004e9754 (diff)
mv643xx_eth: 64bit mib counter read fix
On several mv643xx_eth hardware versions, the two 64bit mib counters for 'good octets received' and 'good octets sent' are actually 32bit counters, and reading from the upper half of the register has the same effect as reading from the lower half of the register: an atomic read-and-clear of the entire 32bit counter value. This can under heavy traffic occasionally lead to small numbers being added to the upper half of the 64bit mib counter even though no 32bit wrap has occured. Since we poll the mib counters at least every 30 seconds anyway, we might as well just skip the reads of the upper halves of the hardware counters without breaking the stats, which this patch does. Signed-off-by: Lennert Buytenhek <buytenh@marvell.com> Cc: stable@kernel.org Signed-off-by: David S. Miller <davem@davemloft.net>
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