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authorChen-Yu Tsai <wens@csie.org>2014-10-20 22:10:28 +0800
committerMaxime Ripard <maxime.ripard@free-electrons.com>2014-10-21 21:47:34 +0200
commit0b0f08028e4e2d69edbe4bb073af26cd17505a04 (patch)
tree17aef4828848ef4c2e971e4482db5367664f2211 /Documentation/rapidio
parent3b2bd70f03c75d37de791b65d574a31d1e2507b0 (diff)
clk: sunxi: Add support for bus clock gates on Allwinner A80 SoC
This adds the gate clocks for AHB/APB busses on the A80 SoC. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
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