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authorLinus Torvalds <torvalds@linux-foundation.org>2013-09-04 08:38:26 -0700
committerLinus Torvalds <torvalds@linux-foundation.org>2013-09-04 08:38:26 -0700
commitac3c1c4f1c77190408162aee559c655090597072 (patch)
tree6c0e1ddbada6d6dbfb59b7f8d766dfd38b7321f1 /Documentation
parent5e0b3a4e88012d259e8b2c0f02f393c79686daf9 (diff)
parentcfb6d656d569510ac9239583ce09e4c92ad54719 (diff)
Merge branch 'timers-core-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip
Pull timer changes from Ingo Molnar: "Various clocksource driver updates: extend the core with memory mapped hardware (mmio) support and add new (ARM) Moxart SoC and sun4i hardware support" * 'timers-core-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: (23 commits) clocksource: arch_timer: Add support for memory mapped timers clocksource: arch_timer: Push the read/write wrappers deeper Documentation: Add memory mapped ARM architected timer binding clocksource: arch_timer: Pass clock event to set_mode callback clocksource: arch_timer: Make register accessors less error-prone ARM: clocksource: moxart: documentation: Update device tree bindings document ARM: clocksource: moxart: Add bitops.h include ARM: clocksource: moxart: documentation: Fix device tree bindings document ARM: clocksource: Add support for MOXA ART SoCs clocksource: cadence_ttc: Reuse clocksource as sched_clock clocksource: cadence_ttc: Remove unused header clocksource: sun4i: Fix bug when switching from periodic to oneshot modes clocksource: sun4i: Cleanup parent clock setup clocksource: sun4i: Remove TIMER_SCAL variable clocksource: sun4i: Factor out some timer code clocksource: sun4i: Fix the next event code clocksource: sun4i: Don't forget to enable the clock we use clocksource: sun4i: Add clocksource and sched clock drivers clocksource: sun4i: rename AUTORELOAD define to RELOAD clocksource: sun4i: Wrap macros arguments in parenthesis ...
Diffstat (limited to 'Documentation')
-rw-r--r--Documentation/devicetree/bindings/arm/arch_timer.txt59
-rw-r--r--Documentation/devicetree/bindings/timer/moxa,moxart-timer.txt17
2 files changed, 73 insertions, 3 deletions
diff --git a/Documentation/devicetree/bindings/arm/arch_timer.txt b/Documentation/devicetree/bindings/arm/arch_timer.txt
index 20746e5abe6f..06fc7602593a 100644
--- a/Documentation/devicetree/bindings/arm/arch_timer.txt
+++ b/Documentation/devicetree/bindings/arm/arch_timer.txt
@@ -1,10 +1,14 @@
* ARM architected timer
-ARM cores may have a per-core architected timer, which provides per-cpu timers.
+ARM cores may have a per-core architected timer, which provides per-cpu timers,
+or a memory mapped architected timer, which provides up to 8 frames with a
+physical and optional virtual timer per frame.
-The timer is attached to a GIC to deliver its per-processor interrupts.
+The per-core architected timer is attached to a GIC to deliver its
+per-processor interrupts via PPIs. The memory mapped timer is attached to a GIC
+to deliver its interrupts via SPIs.
-** Timer node properties:
+** CP15 Timer node properties:
- compatible : Should at least contain one of
"arm,armv7-timer"
@@ -26,3 +30,52 @@ Example:
<1 10 0xf08>;
clock-frequency = <100000000>;
};
+
+** Memory mapped timer node properties:
+
+- compatible : Should at least contain "arm,armv7-timer-mem".
+
+- clock-frequency : The frequency of the main counter, in Hz. Optional.
+
+- reg : The control frame base address.
+
+Note that #address-cells, #size-cells, and ranges shall be present to ensure
+the CPU can address a frame's registers.
+
+A timer node has up to 8 frame sub-nodes, each with the following properties:
+
+- frame-number: 0 to 7.
+
+- interrupts : Interrupt list for physical and virtual timers in that order.
+ The virtual timer interrupt is optional.
+
+- reg : The first and second view base addresses in that order. The second view
+ base address is optional.
+
+- status : "disabled" indicates the frame is not available for use. Optional.
+
+Example:
+
+ timer@f0000000 {
+ compatible = "arm,armv7-timer-mem";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+ reg = <0xf0000000 0x1000>;
+ clock-frequency = <50000000>;
+
+ frame@f0001000 {
+ frame-number = <0>
+ interrupts = <0 13 0x8>,
+ <0 14 0x8>;
+ reg = <0xf0001000 0x1000>,
+ <0xf0002000 0x1000>;
+ };
+
+ frame@f0003000 {
+ frame-number = <1>
+ interrupts = <0 15 0x8>;
+ reg = <0xf0003000 0x1000>;
+ status = "disabled";
+ };
+ };
diff --git a/Documentation/devicetree/bindings/timer/moxa,moxart-timer.txt b/Documentation/devicetree/bindings/timer/moxa,moxart-timer.txt
new file mode 100644
index 000000000000..da2d510cae47
--- /dev/null
+++ b/Documentation/devicetree/bindings/timer/moxa,moxart-timer.txt
@@ -0,0 +1,17 @@
+MOXA ART timer
+
+Required properties:
+
+- compatible : Must be "moxa,moxart-timer"
+- reg : Should contain registers location and length
+- interrupts : Should contain the timer interrupt number
+- clocks : Should contain phandle for the clock that drives the counter
+
+Example:
+
+ timer: timer@98400000 {
+ compatible = "moxa,moxart-timer";
+ reg = <0x98400000 0x42>;
+ interrupts = <19 1>;
+ clocks = <&coreclk>;
+ };

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