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authorMengdong Lin <mengdong.lin@intel.com>2014-06-26 18:45:16 +0800
committerTakashi Iwai <tiwai@suse.de>2014-06-26 15:47:42 +0200
commita07187c992be945ab561b370cbb49cfd72064c3c (patch)
tree2db9f7483d06befd0b159f3b08450eba06e712ab /drivers
parent92a586bdc06de6629dae1b357dac221253f55ff8 (diff)
ALSA: hda - restore BCLK M/N values when resuming HSW/BDW display controller
For Intel Haswell/Broadwell display HD-A controller, the 24MHz HD-A link BCLK is converted from Core Display Clock (CDCLK): BCLK = CDCLK * M / N And there are two registers EM4 and EM5 to program M, N value respectively. The EM4/EM5 values will be lost and when the display power well is disabled. BIOS programs CDCLK selected by OEM and EM4/EM5, but BIOS has no idea about display power well on/off at runtime. So the M/N can be wrong if non-default CDCLK is used when the audio controller resumes, which results in an invalid BCLK and abnormal audio playback rate. So this patch saves and restores valid M/N values on controller suspend/resume. And 'struct hda_intel' is defined to contain standard HD-A 'struct azx' and Intel specific fields, as Takashi suggested. Signed-off-by: Mengdong Lin <mengdong.lin@intel.com> Cc: <stable@vger.kernel.org> Signed-off-by: Takashi Iwai <tiwai@suse.de>
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