path: root/drivers
diff options
authorJani Nikula <jani.nikula@intel.com>2014-07-04 10:00:37 +0800
committerTakashi Iwai <tiwai@suse.de>2014-07-04 07:46:09 +0200
commitc149dcb5c60bfea8871f16dfcc0690255eeb825f (patch)
treef117d9197504d5b02fa0d66d685c556ed30b5489 /drivers
parenta12137e779e17413f87026202a890f8143858259 (diff)
drm/i915: provide interface for audio driver to query cdclk
For Haswell and Broadwell, if the display power well has been disabled, the display audio controller divider values EM4 M VALUE and EM5 N VALUE will have been lost. The CDCLK frequency is required for reprogramming them to generate 24MHz HD-A link BCLK. So provide a private interface for the audio driver to query CDCLK. This is a stopgap solution until a more generic interface between audio and display drivers has been implemented. Signed-off-by: Jani Nikula <jani.nikula@intel.com> Reviewed-by: Damien Lespiau <damien.lespiau@intel.com> Signed-off-by: Mengdong Lin <mengdong.lin@intel.com> Cc: <stable@vger.kernel.org> Signed-off-by: Takashi Iwai <tiwai@suse.de>
Diffstat (limited to 'drivers')
1 files changed, 21 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 6463f0201cf2..409d62676854 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -6053,6 +6053,27 @@ int i915_release_power_well(void)
+ * Private interface for the audio driver to get CDCLK in kHz.
+ *
+ * Caller must request power well using i915_request_power_well() prior to
+ * making the call.
+ */
+int i915_get_cdclk_freq(void)
+ struct drm_i915_private *dev_priv;
+ if (!hsw_pwr)
+ return -ENODEV;
+ dev_priv = container_of(hsw_pwr, struct drm_i915_private,
+ power_domains);
+ return intel_ddi_get_cdclk_freq(dev_priv);

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