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authorJani Nikula <jani.nikula@intel.com>2014-07-04 10:00:37 +0800
committerTakashi Iwai <tiwai@suse.de>2014-07-04 07:46:09 +0200
commitc149dcb5c60bfea8871f16dfcc0690255eeb825f (patch)
treef117d9197504d5b02fa0d66d685c556ed30b5489 /include
parenta12137e779e17413f87026202a890f8143858259 (diff)
drm/i915: provide interface for audio driver to query cdclk
For Haswell and Broadwell, if the display power well has been disabled, the display audio controller divider values EM4 M VALUE and EM5 N VALUE will have been lost. The CDCLK frequency is required for reprogramming them to generate 24MHz HD-A link BCLK. So provide a private interface for the audio driver to query CDCLK. This is a stopgap solution until a more generic interface between audio and display drivers has been implemented. Signed-off-by: Jani Nikula <jani.nikula@intel.com> Reviewed-by: Damien Lespiau <damien.lespiau@intel.com> Signed-off-by: Mengdong Lin <mengdong.lin@intel.com> Cc: <stable@vger.kernel.org> Signed-off-by: Takashi Iwai <tiwai@suse.de>
Diffstat (limited to 'include')
-rw-r--r--include/drm/i915_powerwell.h1
1 files changed, 1 insertions, 0 deletions
diff --git a/include/drm/i915_powerwell.h b/include/drm/i915_powerwell.h
index 2baba9996094..baa6f11b1837 100644
--- a/include/drm/i915_powerwell.h
+++ b/include/drm/i915_powerwell.h
@@ -32,5 +32,6 @@
/* For use by hda_i915 driver */
extern int i915_request_power_well(void);
extern int i915_release_power_well(void);
+extern int i915_get_cdclk_freq(void);
#endif /* _I915_POWERWELL_H_ */

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