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path: root/Documentation/devicetree/bindings/clock/sunxi.txt
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2014-11-23clk: sunxi: Implement A31 PLL6 as a divs clock for 2x outputChen-Yu Tsai1-2/+17
2014-11-23clk: sunxi: Removed unused/incorrect sun6i-a31-apb2-clk driverChen-Yu Tsai1-1/+0
2014-11-11clk: sunxi: unify APB1 clockEmilio López1-1/+0
2014-10-21clk: sunxi: Add support for bus clock gates on Allwinner A80 SoCChen-Yu Tsai1-0/+5
2014-10-21clk: sunxi: Add support for A80 basic bus clocksChen-Yu Tsai1-0/+5
2014-09-27clk: sunxi: Add sun8i MBUS clock supportChen-Yu Tsai1-0/+1
2014-09-27clk: sunxi: mod0: Introduce MMC proper phase handlingMaxime Ripard1-0/+2
2014-09-27clk: sunxi: Introduce mbus compatibleMaxime Ripard1-0/+1
2014-07-15clk: sunxi: sun6i-a31-apb0-gates: Add A23 APB0 supportChen-Yu Tsai1-0/+1
2014-07-07clk: sunxi: Add A23 APB0 divider clock supportChen-Yu Tsai1-0/+1
2014-07-04clk: sunxi: Add A23 clocks supportChen-Yu Tsai1-0/+5
2014-06-11clk: sunxi: document PRCM clock compatible stringsBoris BREZILLON1-0/+3
2014-06-11clk: sunxi: document new A31 USB clock compatibleEmilio López1-0/+1
2014-02-18clk: sunxi: Add new clock compatiblesMaxime Ripard1-18/+18
2014-02-18clk: sunxi: Add Allwinner A20/A31 GMAC clock unitChen-Yu Tsai1-0/+30
2014-02-18clk: sunxi: Add support for PLL6 on the A31Maxime Ripard1-0/+1
2014-02-18clk: sunxi: Add USB clock register defintionsRoman Byshko1-0/+5
2014-02-03clk: sunxi: update clock-output-names dt binding documentationChen-Yu Tsai1-6/+26
2013-12-28clk: sunxi: Allwinner A20 output clock supportChen-Yu Tsai1-0/+1
2013-12-28clk: sunxi: mod0 supportEmilio López1-1/+4
2013-12-28clk: sunxi: add PLL5 and PLL6 supportEmilio López1-0/+2
2013-12-28clk: sunxi: add gating support to PLL1Emilio López1-1/+1
2013-10-11Documentation: dt: Remove clock gates IDs list for Allwinner SoCsMaxime Ripard1-2/+2
2013-08-26clk: sunxi: Add Allwinner A20 gatesMaxime Ripard1-0/+3
2013-08-26clk: sunxi: Add A31 clocks supportMaxime Ripard1-0/+6
2013-08-26clk: sunxi: Add A10s gatesMaxime Ripard1-0/+3
2013-05-28clk: sun5i: Add compatibles for Allwinner A13Maxime Ripard1-104/+13
2013-04-04clk: sunxi: Add support for AXI, AHB, APB0 and APB1 gatesEmilio López1-1/+108
2013-03-27clk: sunxi: rename compatible stringsEmilio López1-11/+11
2013-03-27clk: arm: sunxi: Add a new clock driver for sunxi SOCsEmilio López1-0/+44

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