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path: root/drivers/clk/sunxi/clk-sunxi.c
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2014-11-23clk: sunxi: Implement A31 PLL6 as a divs clock for 2x outputChen-Yu Tsai1-12/+16
2014-11-23clk: sunxi: Specify number of child clocks for divs clocksChen-Yu Tsai1-2/+9
2014-11-23clk: sunxi: Removed unused/incorrect sun6i-a31-apb2-clk driverChen-Yu Tsai1-7/+0
2014-11-11clk: sunxi: unify APB1 clockEmilio López1-5/+2
2014-10-21clk: sunxi: Add support for bus clock gates on Allwinner A80 SoCChen-Yu Tsai1-0/+31
2014-10-21clk: sunxi: make factors clock mux mask configurableChen-Yu Tsai1-0/+1
2014-09-27clk: sunxi: Move mbus to mod0 fileMaxime Ripard1-57/+0
2014-09-27clk: sunxi: Move mod0 clock to a file of its ownMaxime Ripard1-1/+0
2014-09-27clk: sunxi: Introduce mbus compatibleMaxime Ripard1-0/+1
2014-09-27clk: sunxi: factors: Invert the probing logicMaxime Ripard1-92/+3
2014-09-13clk: sunxi: add correct divider table for sun4i-apb0 clockChen-Yu Tsai1-0/+9
2014-07-28clk: sunxi: add __iomem markings to MMIO pointersEmilio López1-5/+5
2014-07-04clk: sunxi: Add A23 clocks supportChen-Yu Tsai1-0/+101
2014-07-04clk: sunxi: Add support for table-based divider clocksChen-Yu Tsai1-4/+5
2014-07-04clk: sunxi: move "ahb_sdram" to protected clock listChen-Yu Tsai1-5/+3
2014-07-04clk: sunxi: register clock gates with clkdevChen-Yu Tsai1-0/+1
2014-06-11clk: sun6i: Protect SDRAM gating bitMaxime Ripard1-0/+1
2014-06-11clk: sun6i: Protect CPU clockMaxime Ripard1-0/+1
2014-06-11clk: sunxi: Rework clock protection codeMaxime Ripard1-28/+44
2014-06-11clk: sunxi: Move the GMAC clock to a file of its ownMaxime Ripard1-98/+0
2014-06-11clk: sunxi: Move the 24M oscillator to a file of its ownMaxime Ripard1-57/+0
2014-06-11clk: sunxi: Remove calls to clk_putMaxime Ripard1-6/+2
2014-06-11clk: sunxi: Implement A31 USB clockMaxime Ripard1-0/+6
2014-06-07Merge tag 'clk-for-linus-3.16' of git://git.linaro.org/people/mike.turquette/...Linus Torvalds1-0/+37
2014-05-20clk: sunxi: fix function type for CLK_OF_DECLARERob Herring1-1/+1
2014-05-20clk: sunxi: avoid double DT matchingRob Herring1-2/+1
2014-05-14clk: sunxi: Fixup clk_sunxi_mmc_phase_control to take a clk rather then a hw_clkHans de Goede1-1/+2
2014-05-05clk: sunxi: Implement MMC phase controlEmilio López1-0/+36
2014-03-19clk: sunxi: fix thinko in commentEmilio López1-1/+1
2014-03-19clk: sunxi: fix some calculationsEmilio López1-3/+3
2014-03-19clk: sunxi: fix A20 PLL4 calculationEmilio López1-0/+7
2014-02-18clk: sunxi: Add new clock compatiblesMaxime Ripard1-15/+15
2014-02-18clk: sunxi: Add Allwinner A20/A31 GMAC clock unitChen-Yu Tsai1-0/+96
2014-02-18clk: sunxi: Add support for PLL6 on the A31Maxime Ripard1-0/+45
2014-02-18clk: sunxi: Add USB clock register defintionsRoman Byshko1-0/+12
2014-02-18clk: sunxi: Add support for USB clock-register reset bitsHans de Goede1-0/+71
2014-02-03clk: sunxi: get divs parent clock name from parent factor clockChen-Yu Tsai1-1/+2
2014-02-03clk: sunxi: add names for pll5, pll6 parent clocks to factors_dataChen-Yu Tsai1-9/+18
2014-02-03clk: sunxi: add clock-output-names dt property supportChen-Yu Tsai1-0/+6
2014-01-27clk: sunxi: fix overflow when setting up divided factorsEmilio López1-1/+1
2013-12-28clk: sunxi: Allwinner A20 output clock supportChen-Yu Tsai1-0/+57
2013-12-28clk: sunxi: support better factor DT nodesEmilio López1-0/+9
2013-12-28clk: sunxi: mod0 supportEmilio López1-0/+57
2013-12-28clk: sunxi: add PLL5 and PLL6 supportEmilio López1-0/+230
2013-12-28clk: sunxi: make factors_clk_setup return the clock it registersEmilio López1-7/+8
2013-12-28clk: sunxi: add gating support to PLL1Emilio López1-0/+2
2013-12-28clk: sunxi: clean the magic number of mux parentsEmilio López1-2/+3
2013-12-28clk: sunxi: register factors clocks behind compositeEmilio López1-4/+66
2013-12-01Merge tag 'sunxi-clk-for-3.13' of https://github.com/mripard/linux into clk-n...Mike Turquette1-12/+46
2013-11-10drivers: clk: sunxi: Fix memory leakage in clk-sunxi.cVictor N. Ramos Mello1-11/+17

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