aboutsummaryrefslogtreecommitdiffstats
path: root/Documentation/devicetree/bindings/clock/sunxi.txt
blob: 91a748fed13d0c540084781ee8cd68491d4f5bfd (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
Device Tree Clock bindings for arch-sunxi

This binding uses the common clock binding[1].

[1] Documentation/devicetree/bindings/clock/clock-bindings.txt

Required properties:
- compatible : shall be one of the following:
	"allwinner,sun4i-osc-clk" - for a gatable oscillator
	"allwinner,sun4i-pll1-clk" - for the main PLL clock
	"allwinner,sun6i-a31-pll1-clk" - for the main PLL clock on A31
	"allwinner,sun4i-cpu-clk" - for the CPU multiplexer clock
	"allwinner,sun4i-axi-clk" - for the AXI clock
	"allwinner,sun4i-axi-gates-clk" - for the AXI gates
	"allwinner,sun4i-ahb-clk" - for the AHB clock
	"allwinner,sun4i-ahb-gates-clk" - for the AHB gates on A10
	"allwinner,sun5i-a13-ahb-gates-clk" - for the AHB gates on A13
	"allwinner,sun5i-a10s-ahb-gates-clk" - for the AHB gates on A10s
	"allwinner,sun7i-a20-ahb-gates-clk" - for the AHB gates on A20
	"allwinner,sun6i-a31-ahb1-mux-clk" - for the AHB1 multiplexer on A31
	"allwinner,sun6i-a31-ahb1-gates-clk" - for the AHB1 gates on A31
	"allwinner,sun4i-apb0-clk" - for the APB0 clock
	"allwinner,sun4i-apb0-gates-clk" - for the APB0 gates on A10
	"allwinner,sun5i-a13-apb0-gates-clk" - for the APB0 gates on A13
	"allwinner,sun5i-a10s-apb0-gates-clk" - for the APB0 gates on A10s
	"allwinner,sun7i-a20-apb0-gates-clk" - for the APB0 gates on A20
	"allwinner,sun4i-apb1-clk" - for the APB1 clock
	"allwinner,sun4i-apb1-mux-clk" - for the APB1 clock muxing
	"allwinner,sun4i-apb1-gates-clk" - for the APB1 gates on A10
	"allwinner,sun5i-a13-apb1-gates-clk" - for the APB1 gates on A13
	"allwinner,sun5i-a10s-apb1-gates-clk" - for the APB1 gates on A10s
	"allwinner,sun6i-a31-apb1-gates-clk" - for the APB1 gates on A31
	"allwinner,sun7i-a20-apb1-gates-clk" - for the APB1 gates on A20
	"allwinner,sun6i-a31-apb2-div-clk" - for the APB2 gates on A31
	"allwinner,sun6i-a31-apb2-gates-clk" - for the APB2 gates on A31

Required properties for all clocks:
- reg : shall be the control register address for the clock.
- clocks : shall be the input parent clock(s) phandle for the clock
- #clock-cells : from common clock binding; shall be set to 0 except for
	"allwinner,*-gates-clk" where it shall be set to 1

Additionally, "allwinner,*-gates-clk" clocks require:
- clock-output-names : the corresponding gate names that the clock controls

Clock consumers should specify the desired clocks they use with a
"clocks" phandle cell. Consumers that are using a gated clock should
provide an additional ID in their clock property. This ID is the
offset of the bit controlling this particular gate in the register.

For example:

osc24M: osc24M@01c20050 {
	#clock-cells = <0>;
	compatible = "allwinner,sun4i-osc-clk";
	reg = <0x01c20050 0x4>;
	clocks = <&osc24M_fixed>;
};

pll1: pll1@01c20000 {
	#clock-cells = <0>;
	compatible = "allwinner,sun4i-pll1-clk";
	reg = <0x01c20000 0x4>;
	clocks = <&osc24M>;
};

cpu: cpu@01c20054 {
	#clock-cells = <0>;
	compatible = "allwinner,sun4i-cpu-clk";
	reg = <0x01c20054 0x4>;
	clocks = <&osc32k>, <&osc24M>, <&pll1>;
};

Privacy Policy