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NVIDIA Tegra host1x

Required properties:
- compatible: "nvidia,tegra<chip>-host1x"
- reg: Physical base address and length of the controller's registers.
- interrupts: The interrupt outputs from the controller.
- #address-cells: The number of cells used to represent physical base addresses
  in the host1x address space. Should be 1.
- #size-cells: The number of cells used to represent the size of an address
  range in the host1x address space. Should be 1.
- ranges: The mapping of the host1x address space to the CPU address space.
- clocks: Must contain one entry, for the module clock.
  See ../clocks/clock-bindings.txt for details.

The host1x top-level node defines a number of children, each representing one
of the following host1x client modules:

- mpe: video encoder

  Required properties:
  - compatible: "nvidia,tegra<chip>-mpe"
  - reg: Physical base address and length of the controller's registers.
  - interrupts: The interrupt outputs from the controller.
  - clocks: Must contain one entry, for the module clock.
    See ../clocks/clock-bindings.txt for details.

- vi: video input

  Required properties:
  - compatible: "nvidia,tegra<chip>-vi"
  - reg: Physical base address and length of the controller's registers.
  - interrupts: The interrupt outputs from the controller.
  - clocks: Must contain one entry, for the module clock.
    See ../clocks/clock-bindings.txt for details.

- epp: encoder pre-processor

  Required properties:
  - compatible: "nvidia,tegra<chip>-epp"
  - reg: Physical base address and length of the controller's registers.
  - interrupts: The interrupt outputs from the controller.
  - clocks: Must contain one entry, for the module clock.
    See ../clocks/clock-bindings.txt for details.

- isp: image signal processor

  Required properties:
  - compatible: "nvidia,tegra<chip>-isp"
  - reg: Physical base address and length of the controller's registers.
  - interrupts: The interrupt outputs from the controller.
  - clocks: Must contain one entry, for the module clock.
    See ../clocks/clock-bindings.txt for details.

- gr2d: 2D graphics engine

  Required properties:
  - compatible: "nvidia,tegra<chip>-gr2d"
  - reg: Physical base address and length of the controller's registers.
  - interrupts: The interrupt outputs from the controller.
  - clocks: Must contain one entry, for the module clock.
    See ../clocks/clock-bindings.txt for details.

- gr3d: 3D graphics engine

  Required properties:
  - compatible: "nvidia,tegra<chip>-gr3d"
  - reg: Physical base address and length of the controller's registers.
  - clocks: Must contain an entry for each entry in clock-names.
    See ../clocks/clock-bindings.txt for details.
  - clock-names: Must include the following entries:
    (This property may be omitted if the only clock in the list is "3d")
    - 3d
      This MUST be the first entry.
    - 3d2 (Only required on SoCs with two 3D clocks)

- dc: display controller

  Required properties:
  - compatible: "nvidia,tegra<chip>-dc"
  - reg: Physical base address and length of the controller's registers.
  - interrupts: The interrupt outputs from the controller.
  - clocks: Must contain an entry for each entry in clock-names.
    See ../clocks/clock-bindings.txt for details.
  - clock-names: Must include the following entries:
    - dc
      This MUST be the first entry.
    - parent

  Each display controller node has a child node, named "rgb", that represents
  the RGB output associated with the controller. It can take the following
  optional properties:
  - nvidia,ddc-i2c-bus: phandle of an I2C controller used for DDC EDID probing
  - nvidia,hpd-gpio: specifies a GPIO used for hotplug detection
  - nvidia,edid: supplies a binary EDID blob

- hdmi: High Definition Multimedia Interface

  Required properties:
  - compatible: "nvidia,tegra<chip>-hdmi"
  - reg: Physical base address and length of the controller's registers.
  - interrupts: The interrupt outputs from the controller.
  - vdd-supply: regulator for supply voltage
  - pll-supply: regulator for PLL
  - clocks: Must contain an entry for each entry in clock-names.
    See ../clocks/clock-bindings.txt for details.
  - clock-names: Must include the following entries:
    - hdmi
      This MUST be the first entry.
    - parent

  Optional properties:
  - nvidia,ddc-i2c-bus: phandle of an I2C controller used for DDC EDID probing
  - nvidia,hpd-gpio: specifies a GPIO used for hotplug detection
  - nvidia,edid: supplies a binary EDID blob

- tvo: TV encoder output

  Required properties:
  - compatible: "nvidia,tegra<chip>-tvo"
  - reg: Physical base address and length of the controller's registers.
  - interrupts: The interrupt outputs from the controller.
  - clocks: Must contain one entry, for the module clock.
    See ../clocks/clock-bindings.txt for details.

- dsi: display serial interface

  Required properties:
  - compatible: "nvidia,tegra<chip>-dsi"
  - reg: Physical base address and length of the controller's registers.
  - clocks: Must contain an entry for each entry in clock-names.
    See ../clocks/clock-bindings.txt for details.
  - clock-names: Must include the following entries:
    - dsi
      This MUST be the first entry.
    - parent

Example:

/ {
	...

	host1x {
		compatible = "nvidia,tegra20-host1x", "simple-bus";
		reg = <0x50000000 0x00024000>;
		interrupts = <0 65 0x04   /* mpcore syncpt */
			      0 67 0x04>; /* mpcore general */
		clocks = <&tegra_car TEGRA20_CLK_HOST1X>;

		#address-cells = <1>;
		#size-cells = <1>;

		ranges = <0x54000000 0x54000000 0x04000000>;

		mpe {
			compatible = "nvidia,tegra20-mpe";
			reg = <0x54040000 0x00040000>;
			interrupts = <0 68 0x04>;
			clocks = <&tegra_car TEGRA20_CLK_MPE>;
		};

		vi {
			compatible = "nvidia,tegra20-vi";
			reg = <0x54080000 0x00040000>;
			interrupts = <0 69 0x04>;
			clocks = <&tegra_car TEGRA20_CLK_VI>;
		};

		epp {
			compatible = "nvidia,tegra20-epp";
			reg = <0x540c0000 0x00040000>;
			interrupts = <0 70 0x04>;
			clocks = <&tegra_car TEGRA20_CLK_EPP>;
		};

		isp {
			compatible = "nvidia,tegra20-isp";
			reg = <0x54100000 0x00040000>;
			interrupts = <0 71 0x04>;
			clocks = <&tegra_car TEGRA20_CLK_ISP>;
		};

		gr2d {
			compatible = "nvidia,tegra20-gr2d";
			reg = <0x54140000 0x00040000>;
			interrupts = <0 72 0x04>;
			clocks = <&tegra_car TEGRA20_CLK_GR2D>;
		};

		gr3d {
			compatible = "nvidia,tegra20-gr3d";
			reg = <0x54180000 0x00040000>;
			clocks = <&tegra_car TEGRA20_CLK_GR3D>;
		};

		dc@54200000 {
			compatible = "nvidia,tegra20-dc";
			reg = <0x54200000 0x00040000>;
			interrupts = <0 73 0x04>;
			clocks = <&tegra_car TEGRA20_CLK_DISP1>,
				 <&tegra_car TEGRA20_CLK_PLL_P>;
			clock-names = "disp1", "parent";

			rgb {
				status = "disabled";
			};
		};

		dc@54240000 {
			compatible = "nvidia,tegra20-dc";
			reg = <0x54240000 0x00040000>;
			interrupts = <0 74 0x04>;
			clocks = <&tegra_car TEGRA20_CLK_DISP2>,
				 <&tegra_car TEGRA20_CLK_PLL_P>;
			clock-names = "disp2", "parent";

			rgb {
				status = "disabled";
			};
		};

		hdmi {
			compatible = "nvidia,tegra20-hdmi";
			reg = <0x54280000 0x00040000>;
			interrupts = <0 75 0x04>;
			clocks = <&tegra_car TEGRA20_CLK_HDMI>,
				 <&tegra_car TEGRA20_CLK_PLL_D_OUT0>;
			clock-names = "hdmi", "parent";
			status = "disabled";
		};

		tvo {
			compatible = "nvidia,tegra20-tvo";
			reg = <0x542c0000 0x00040000>;
			interrupts = <0 76 0x04>;
			clocks = <&tegra_car TEGRA20_CLK_TVO>;
			status = "disabled";
		};

		dsi {
			compatible = "nvidia,tegra20-dsi";
			reg = <0x54300000 0x00040000>;
			clocks = <&tegra_car TEGRA20_CLK_DSI>,
				 <&tegra_car TEGRA20_CLK_PLL_D_OUT0>;
			clock-names = "dsi", "parent";
			status = "disabled";
		};
	};

	...
};

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