aboutsummaryrefslogtreecommitdiffstats
path: root/drivers/staging/octeon/cvmx-pcsxx-defs.h
blob: 55d120fe8aedf460cb1e11cb9dfd7b128ea7b08b (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
/***********************license start***************
 * Author: Cavium Networks
 *
 * Contact: support@caviumnetworks.com
 * This file is part of the OCTEON SDK
 *
 * Copyright (c) 2003-2008 Cavium Networks
 *
 * This file is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License, Version 2, as
 * published by the Free Software Foundation.
 *
 * This file is distributed in the hope that it will be useful, but
 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
 * NONINFRINGEMENT.  See the GNU General Public License for more
 * details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this file; if not, write to the Free Software
 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
 * or visit http://www.gnu.org/licenses/.
 *
 * This file may also be available under a different license from Cavium.
 * Contact Cavium Networks for more information
 ***********************license end**************************************/

#ifndef __CVMX_PCSXX_DEFS_H__
#define __CVMX_PCSXX_DEFS_H__

#define CVMX_PCSXX_10GBX_STATUS_REG(block_id) \
	 CVMX_ADD_IO_SEG(0x00011800B0000828ull + (((block_id) & 1) * 0x8000000ull))
#define CVMX_PCSXX_BIST_STATUS_REG(block_id) \
	 CVMX_ADD_IO_SEG(0x00011800B0000870ull + (((block_id) & 1) * 0x8000000ull))
#define CVMX_PCSXX_BIT_LOCK_STATUS_REG(block_id) \
	 CVMX_ADD_IO_SEG(0x00011800B0000850ull + (((block_id) & 1) * 0x8000000ull))
#define CVMX_PCSXX_CONTROL1_REG(block_id) \
	 CVMX_ADD_IO_SEG(0x00011800B0000800ull + (((block_id) & 1) * 0x8000000ull))
#define CVMX_PCSXX_CONTROL2_REG(block_id) \
	 CVMX_ADD_IO_SEG(0x00011800B0000818ull + (((block_id) & 1) * 0x8000000ull))
#define CVMX_PCSXX_INT_EN_REG(block_id) \
	 CVMX_ADD_IO_SEG(0x00011800B0000860ull + (((block_id) & 1) * 0x8000000ull))
#define CVMX_PCSXX_INT_REG(block_id) \
	 CVMX_ADD_IO_SEG(0x00011800B0000858ull + (((block_id) & 1) * 0x8000000ull))
#define CVMX_PCSXX_LOG_ANL_REG(block_id) \
	 CVMX_ADD_IO_SEG(0x00011800B0000868ull + (((block_id) & 1) * 0x8000000ull))
#define CVMX_PCSXX_MISC_CTL_REG(block_id) \
	 CVMX_ADD_IO_SEG(0x00011800B0000848ull + (((block_id) & 1) * 0x8000000ull))
#define CVMX_PCSXX_RX_SYNC_STATES_REG(block_id) \
	 CVMX_ADD_IO_SEG(0x00011800B0000838ull + (((block_id) & 1) * 0x8000000ull))
#define CVMX_PCSXX_SPD_ABIL_REG(block_id) \
	 CVMX_ADD_IO_SEG(0x00011800B0000810ull + (((block_id) & 1) * 0x8000000ull))
#define CVMX_PCSXX_STATUS1_REG(block_id) \
	 CVMX_ADD_IO_SEG(0x00011800B0000808ull + (((block_id) & 1) * 0x8000000ull))
#define CVMX_PCSXX_STATUS2_REG(block_id) \
	 CVMX_ADD_IO_SEG(0x00011800B0000820ull + (((block_id) & 1) * 0x8000000ull))
#define CVMX_PCSXX_TX_RX_POLARITY_REG(block_id) \
	 CVMX_ADD_IO_SEG(0x00011800B0000840ull + (((block_id) & 1) * 0x8000000ull))
#define CVMX_PCSXX_TX_RX_STATES_REG(block_id) \
	 CVMX_ADD_IO_SEG(0x00011800B0000830ull + (((block_id) & 1) * 0x8000000ull))

union cvmx_pcsxx_10gbx_status_reg {
	uint64_t u64;
	struct cvmx_pcsxx_10gbx_status_reg_s {
		uint64_t reserved_13_63:51;
		uint64_t alignd:1;
		uint64_t pattst:1;
		uint64_t reserved_4_10:7;
		uint64_t l3sync:1;
		uint64_t l2sync:1;
		uint64_t l1sync:1;
		uint64_t l0sync:1;
	} s;
	struct cvmx_pcsxx_10gbx_status_reg_s cn52xx;
	struct cvmx_pcsxx_10gbx_status_reg_s cn52xxp1;
	struct cvmx_pcsxx_10gbx_status_reg_s cn56xx;
	struct cvmx_pcsxx_10gbx_status_reg_s cn56xxp1;
};

union cvmx_pcsxx_bist_status_reg {
	uint64_t u64;
	struct cvmx_pcsxx_bist_status_reg_s {
		uint64_t reserved_1_63:63;
		uint64_t bist_status:1;
	} s;
	struct cvmx_pcsxx_bist_status_reg_s cn52xx;
	struct cvmx_pcsxx_bist_status_reg_s cn52xxp1;
	struct cvmx_pcsxx_bist_status_reg_s cn56xx;
	struct cvmx_pcsxx_bist_status_reg_s cn56xxp1;
};

union cvmx_pcsxx_bit_lock_status_reg {
	uint64_t u64;
	struct cvmx_pcsxx_bit_lock_status_reg_s {
		uint64_t reserved_4_63:60;
		uint64_t bitlck3:1;
		uint64_t bitlck2:1;
		uint64_t bitlck1:1;
		uint64_t bitlck0:1;
	} s;
	struct cvmx_pcsxx_bit_lock_status_reg_s cn52xx;
	struct cvmx_pcsxx_bit_lock_status_reg_s cn52xxp1;
	struct cvmx_pcsxx_bit_lock_status_reg_s cn56xx;
	struct cvmx_pcsxx_bit_lock_status_reg_s cn56xxp1;
};

union cvmx_pcsxx_control1_reg {
	uint64_t u64;
	struct cvmx_pcsxx_control1_reg_s {
		uint64_t reserved_16_63:48;
		uint64_t reset:1;
		uint64_t loopbck1:1;
		uint64_t spdsel1:1;
		uint64_t reserved_12_12:1;
		uint64_t lo_pwr:1;
		uint64_t reserved_7_10:4;
		uint64_t spdsel0:1;
		uint64_t spd:4;
		uint64_t reserved_0_1:2;
	} s;
	struct cvmx_pcsxx_control1_reg_s cn52xx;
	struct cvmx_pcsxx_control1_reg_s cn52xxp1;
	struct cvmx_pcsxx_control1_reg_s cn56xx;
	struct cvmx_pcsxx_control1_reg_s cn56xxp1;
};

union cvmx_pcsxx_control2_reg {
	uint64_t u64;
	struct cvmx_pcsxx_control2_reg_s {
		uint64_t reserved_2_63:62;
		uint64_t type:2;
	} s;
	struct cvmx_pcsxx_control2_reg_s cn52xx;
	struct cvmx_pcsxx_control2_reg_s cn52xxp1;
	struct cvmx_pcsxx_control2_reg_s cn56xx;
	struct cvmx_pcsxx_control2_reg_s cn56xxp1;
};

union cvmx_pcsxx_int_en_reg {
	uint64_t u64;
	struct cvmx_pcsxx_int_en_reg_s {
		uint64_t reserved_6_63:58;
		uint64_t algnlos_en:1;
		uint64_t synlos_en:1;
		uint64_t bitlckls_en:1;
		uint64_t rxsynbad_en:1;
		uint64_t rxbad_en:1;
		uint64_t txflt_en:1;
	} s;
	struct cvmx_pcsxx_int_en_reg_s cn52xx;
	struct cvmx_pcsxx_int_en_reg_s cn52xxp1;
	struct cvmx_pcsxx_int_en_reg_s cn56xx;
	struct cvmx_pcsxx_int_en_reg_s cn56xxp1;
};

union cvmx_pcsxx_int_reg {
	uint64_t u64;
	struct cvmx_pcsxx_int_reg_s {
		uint64_t reserved_6_63:58;
		uint64_t algnlos:1;
		uint64_t synlos:1;
		uint64_t bitlckls:1;
		uint64_t rxsynbad:1;
		uint64_t rxbad:1;
		uint64_t txflt:1;
	} s;
	struct cvmx_pcsxx_int_reg_s cn52xx;
	struct cvmx_pcsxx_int_reg_s cn52xxp1;
	struct cvmx_pcsxx_int_reg_s cn56xx;
	struct cvmx_pcsxx_int_reg_s cn56xxp1;
};

union cvmx_pcsxx_log_anl_reg {
	uint64_t u64;
	struct cvmx_pcsxx_log_anl_reg_s {
		uint64_t reserved_7_63:57;
		uint64_t enc_mode:1;
		uint64_t drop_ln:2;
		uint64_t lafifovfl:1;
		uint64_t la_en:1;
		uint64_t pkt_sz:2;
	} s;
	struct cvmx_pcsxx_log_anl_reg_s cn52xx;
	struct cvmx_pcsxx_log_anl_reg_s cn52xxp1;
	struct cvmx_pcsxx_log_anl_reg_s cn56xx;
	struct cvmx_pcsxx_log_anl_reg_s cn56xxp1;
};

union cvmx_pcsxx_misc_ctl_reg {
	uint64_t u64;
	struct cvmx_pcsxx_misc_ctl_reg_s {
		uint64_t reserved_4_63:60;
		uint64_t tx_swap:1;
		uint64_t rx_swap:1;
		uint64_t xaui:1;
		uint64_t gmxeno:1;
	} s;
	struct cvmx_pcsxx_misc_ctl_reg_s cn52xx;
	struct cvmx_pcsxx_misc_ctl_reg_s cn52xxp1;
	struct cvmx_pcsxx_misc_ctl_reg_s cn56xx;
	struct cvmx_pcsxx_misc_ctl_reg_s cn56xxp1;
};

union cvmx_pcsxx_rx_sync_states_reg {
	uint64_t u64;
	struct cvmx_pcsxx_rx_sync_states_reg_s {
		uint64_t reserved_16_63:48;
		uint64_t sync3st:4;
		uint64_t sync2st:4;
		uint64_t sync1st:4;
		uint64_t sync0st:4;
	} s;
	struct cvmx_pcsxx_rx_sync_states_reg_s cn52xx;
	struct cvmx_pcsxx_rx_sync_states_reg_s cn52xxp1;
	struct cvmx_pcsxx_rx_sync_states_reg_s cn56xx;
	struct cvmx_pcsxx_rx_sync_states_reg_s cn56xxp1;
};

union cvmx_pcsxx_spd_abil_reg {
	uint64_t u64;
	struct cvmx_pcsxx_spd_abil_reg_s {
		uint64_t reserved_2_63:62;
		uint64_t tenpasst:1;
		uint64_t tengb:1;
	} s;
	struct cvmx_pcsxx_spd_abil_reg_s cn52xx;
	struct cvmx_pcsxx_spd_abil_reg_s cn52xxp1;
	struct cvmx_pcsxx_spd_abil_reg_s cn56xx;
	struct cvmx_pcsxx_spd_abil_reg_s cn56xxp1;
};

union cvmx_pcsxx_status1_reg {
	uint64_t u64;
	struct cvmx_pcsxx_status1_reg_s {
		uint64_t reserved_8_63:56;
		uint64_t flt:1;
		uint64_t reserved_3_6:4;
		uint64_t rcv_lnk:1;
		uint64_t lpable:1;
		uint64_t reserved_0_0:1;
	} s;
	struct cvmx_pcsxx_status1_reg_s cn52xx;
	struct cvmx_pcsxx_status1_reg_s cn52xxp1;
	struct cvmx_pcsxx_status1_reg_s cn56xx;
	struct cvmx_pcsxx_status1_reg_s cn56xxp1;
};

union cvmx_pcsxx_status2_reg {
	uint64_t u64;
	struct cvmx_pcsxx_status2_reg_s {
		uint64_t reserved_16_63:48;
		uint64_t dev:2;
		uint64_t reserved_12_13:2;
		uint64_t xmtflt:1;
		uint64_t rcvflt:1;
		uint64_t reserved_3_9:7;
		uint64_t tengb_w:1;
		uint64_t tengb_x:1;
		uint64_t tengb_r:1;
	} s;
	struct cvmx_pcsxx_status2_reg_s cn52xx;
	struct cvmx_pcsxx_status2_reg_s cn52xxp1;
	struct cvmx_pcsxx_status2_reg_s cn56xx;
	struct cvmx_pcsxx_status2_reg_s cn56xxp1;
};

union cvmx_pcsxx_tx_rx_polarity_reg {
	uint64_t u64;
	struct cvmx_pcsxx_tx_rx_polarity_reg_s {
		uint64_t reserved_10_63:54;
		uint64_t xor_rxplrt:4;
		uint64_t xor_txplrt:4;
		uint64_t rxplrt:1;
		uint64_t txplrt:1;
	} s;
	struct cvmx_pcsxx_tx_rx_polarity_reg_s cn52xx;
	struct cvmx_pcsxx_tx_rx_polarity_reg_cn52xxp1 {
		uint64_t reserved_2_63:62;
		uint64_t rxplrt:1;
		uint64_t txplrt:1;
	} cn52xxp1;
	struct cvmx_pcsxx_tx_rx_polarity_reg_s cn56xx;
	struct cvmx_pcsxx_tx_rx_polarity_reg_cn52xxp1 cn56xxp1;
};

union cvmx_pcsxx_tx_rx_states_reg {
	uint64_t u64;
	struct cvmx_pcsxx_tx_rx_states_reg_s {
		uint64_t reserved_14_63:50;
		uint64_t term_err:1;
		uint64_t syn3bad:1;
		uint64_t syn2bad:1;
		uint64_t syn1bad:1;
		uint64_t syn0bad:1;
		uint64_t rxbad:1;
		uint64_t algn_st:3;
		uint64_t rx_st:2;
		uint64_t tx_st:3;
	} s;
	struct cvmx_pcsxx_tx_rx_states_reg_s cn52xx;
	struct cvmx_pcsxx_tx_rx_states_reg_cn52xxp1 {
		uint64_t reserved_13_63:51;
		uint64_t syn3bad:1;
		uint64_t syn2bad:1;
		uint64_t syn1bad:1;
		uint64_t syn0bad:1;
		uint64_t rxbad:1;
		uint64_t algn_st:3;
		uint64_t rx_st:2;
		uint64_t tx_st:3;
	} cn52xxp1;
	struct cvmx_pcsxx_tx_rx_states_reg_s cn56xx;
	struct cvmx_pcsxx_tx_rx_states_reg_cn52xxp1 cn56xxp1;
};

#endif

Privacy Policy