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authorAtish Patra <atishp@rivosinc.com>2022-07-22 09:50:44 -0700
committerPalmer Dabbelt <palmer@rivosinc.com>2022-08-11 14:36:06 -0700
commitbf952a290f7a9d818204b9b68e861655f8b15a65 (patch)
tree2dd0eade51f4649e78175fed24a8283d385fe224 /arch
parentf2906aa863381afb0015a9eb7fefad885d4e5a56 (diff)
RISC-V: Add SSTC extension CSR details
This patch just introduces the required CSR fields related to the SSTC extension. Reviewed-by: Anup Patel <anup@brainfault.org> Signed-off-by: Atish Patra <atishp@rivosinc.com> Link: https://lore.kernel.org/r/20220722165047.519994-2-atishp@rivosinc.com Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
Diffstat (limited to 'arch')
-rw-r--r--arch/riscv/include/asm/csr.h5
1 files changed, 5 insertions, 0 deletions
diff --git a/arch/riscv/include/asm/csr.h b/arch/riscv/include/asm/csr.h
index 6d85655e7edf..34f4eaf326c4 100644
--- a/arch/riscv/include/asm/csr.h
+++ b/arch/riscv/include/asm/csr.h
@@ -235,6 +235,9 @@
#define CSR_SIP 0x144
#define CSR_SATP 0x180
+#define CSR_STIMECMP 0x14D
+#define CSR_STIMECMPH 0x15D
+
#define CSR_VSSTATUS 0x200
#define CSR_VSIE 0x204
#define CSR_VSTVEC 0x205
@@ -244,6 +247,8 @@
#define CSR_VSTVAL 0x243
#define CSR_VSIP 0x244
#define CSR_VSATP 0x280
+#define CSR_VSTIMECMP 0x24D
+#define CSR_VSTIMECMPH 0x25D
#define CSR_HSTATUS 0x600
#define CSR_HEDELEG 0x602

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