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authorKan Liang <kan.liang@linux.intel.com>2021-09-28 08:19:03 -0700
committerPeter Zijlstra <peterz@infradead.org>2021-10-01 13:57:54 +0200
commitecc2123e09f9e71ddc6c53d71e283b8ada685fe2 (patch)
tree956ce3c4fd128e56f21b5677f29489d6d5f01bce /arch
parent02d029a41dc986e2d5a77ecca45803857b346829 (diff)
perf/x86/intel: Update event constraints for ICX
According to the latest event list, the event encoding 0xEF is only available on the first 4 counters. Add it into the event constraints table. Fixes: 6017608936c1 ("perf/x86/intel: Add Icelake support") Signed-off-by: Kan Liang <kan.liang@linux.intel.com> Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org> Link: https://lkml.kernel.org/r/1632842343-25862-1-git-send-email-kan.liang@linux.intel.com
Diffstat (limited to 'arch')
-rw-r--r--arch/x86/events/intel/core.c1
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c
index 7011e87be6d0..9a044438072b 100644
--- a/arch/x86/events/intel/core.c
+++ b/arch/x86/events/intel/core.c
@@ -263,6 +263,7 @@ static struct event_constraint intel_icl_event_constraints[] = {
INTEL_EVENT_CONSTRAINT_RANGE(0xa8, 0xb0, 0xf),
INTEL_EVENT_CONSTRAINT_RANGE(0xb7, 0xbd, 0xf),
INTEL_EVENT_CONSTRAINT_RANGE(0xd0, 0xe6, 0xf),
+ INTEL_EVENT_CONSTRAINT(0xef, 0xf),
INTEL_EVENT_CONSTRAINT_RANGE(0xf0, 0xf4, 0xf),
EVENT_CONSTRAINT_END
};

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