path: root/arch/riscv/kernel/traps.c
AgeCommit message (Expand)AuthorFilesLines
2022-10-12RISC-V: Avoid dereferening NULL regs in die()Palmer Dabbelt1-3/+6
2022-08-18riscv: traps: add missing prototypeConor Dooley1-1/+2
2022-07-21RISC-V: Add fast call path of crash_kexec()Xianting Tian1-0/+4
2022-05-11riscv: integrate alternatives better into the main architectureHeiko Stuebner1-1/+1
2021-12-13exit: Add and use make_task_dead.Eric W. Biederman1-1/+1
2021-09-08trap: cleanup trap_init()Kefeng Wang1-5/+0
2021-07-09Merge tag 'riscv-for-linus-5.14-mw0' of git://git.kernel.org/pub/scm/linux/ke...Linus Torvalds1-0/+35
2021-07-06riscv: add VMAP_STACK overflow detectionTong Tiangen1-0/+35
2021-06-10riscv: xip: support runtime trap patchingVitaly Wool1-4/+9
2021-05-06riscv: remove unused handle_exception symbolRouven Czerwinski1-2/+0
2021-05-06Merge tag 'riscv-for-linus-5.13-mw0' of git://git.kernel.org/pub/scm/linux/ke...Linus Torvalds1-1/+1
2021-04-26riscv: add __init section marker to some functionsJisheng Zhang1-1/+1
2021-04-15riscv: add do_page_fault and do_trap_break into the kprobes blacklistJisheng Zhang1-0/+1
2021-03-09riscv: traps: Fix no prototype warningsNanyong Sun1-0/+1
2021-01-14riscv: Add dump stack in show_regsKefeng Wang1-1/+2
2021-01-14riscv: Add uprobes supportedGuo Ren1-0/+10
2021-01-14riscv: Add kprobes supportedGuo Ren1-0/+9
2020-07-30RISC-V: Setup exception vector earlyAtish Patra1-7/+1
2020-06-18maccess: rename probe_kernel_address to get_kernel_nofaultChristoph Hellwig1-2/+2
2020-06-09irqchip: RISC-V per-HART local interrupt controller driverAnup Patel1-2/+0
2020-05-18riscv: Add KGDB supportVincent Chen1-0/+5
2020-04-09Merge tag 'riscv-for-linus-5.7' of git://git.kernel.org/pub/scm/linux/kernel/...Linus Torvalds1-5/+27
2020-04-03riscv: Unaligned load/store handling for M_MODEDamien Le Moal1-3/+24
2020-03-31RISC-V: Add supported for ordered booting method using HSMAtish Patra1-1/+1
2020-03-26riscv: add macro to get instruction lengthZong Li1-1/+2
2020-03-16irqchip/sifive-plic: Enable/Disable external interrupts upon cpu online/offlineAtish Patra1-1/+1
2020-02-18RISC-V: Don't enable all interrupts in trap_init()Anup Patel1-2/+2
2019-11-05riscv: abstract out CSR names for supervisor vs machine modeChristoph Hellwig1-8/+8
2019-10-28riscv: for C functions called only from assembly, mark with __visiblePaul Walmsley1-2/+2
2019-10-28riscv: add missing header file includesPaul Walmsley1-0/+1
2019-10-25riscv: cleanup do_trap_breakChristoph Hellwig1-20/+6
2019-10-14riscv: remove the switch statement in do_trap_break()Vincent Chen1-11/+11
2019-10-07riscv: Correct the handling of unexpected ebreak in do_trap_break()Vincent Chen1-3/+3
2019-10-07riscv: avoid sending a SIGTRAP to a user thread trapped in WARN()Vincent Chen1-1/+1
2019-10-07riscv: avoid kernel hangs when trapped in BUG()Vincent Chen1-3/+3
2019-07-08Merge branch 'siginfo-linus' of git://git.kernel.org/pub/scm/linux/kernel/git...Linus Torvalds1-5/+6
2019-06-05treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 286Thomas Gleixner1-9/+1
2019-05-29signal: Remove the task parameter from force_sig_faultEric W. Biederman1-2/+2
2019-05-29signal: Explicitly call force_sig_fault on currentEric W. Biederman1-1/+1
2019-05-29signal/riscv: Remove tsk parameter from do_trapEric W. Biederman1-3/+4
2019-05-16riscv: Support BUG() in kernel moduleVincent Chen1-1/+1
2019-05-16riscv: Add the support for c.ebreak check in is_valid_bugaddr()Vincent Chen1-3/+17
2019-05-16RISC-V: Access CSRs using CSR numbersAnup Patel1-3/+3
2019-04-25riscv: remove duplicate macros from ptrace.hChristoph Hellwig1-1/+1
2018-08-13RISC-V: Don't increment sepc after breakpoint.Jim Wilson1-1/+0
2018-06-16Merge tag 'riscv-for-linus-4.18-merge_window' of git://git.kernel.org/pub/scm...Linus Torvalds1-1/+1
2018-06-07riscv: no __user for probe_kernel_address()Luc Van Oostenryck1-1/+1
2018-04-25signal/riscv: Replace do_trap_siginfo with force_sig_faultEric W. Biederman1-8/+2
2018-04-25signal/riscv: Use force_sig_fault where appropriateEric W. Biederman1-8/+1
2018-04-25signal: Ensure every siginfo we send has all bits initializedEric W. Biederman1-0/+1

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